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standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use i pm5365 temap vt/tu mapper and m13 multiplexer data sheet proprietary and confidential released issue 3: september 2001
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use ii contents 1 features...............................................................................................1 2 applications...................................................................................... 11 3 references .......................................................................................12 4 application examples ....................................................................16 5 block diagram..................................................................................17 5.1 top level block diagram...................................................17 5.2 vt/tu mapper only mode block diagram......................19 5.3 ds3 framer only block diagram.....................................20 6 description .......................................................................................21 7 pin diagram ........................................................................................25 8 pin description ................................................................................26 9 functional description ...............................................................57 9.1 t1 framer (t1-frmr)..............................................................57 9.2 e1 framer (e1-frmr) .............................................................57 9.3 performance monitor counters (t1/e1-pmon) .........64 9.4 t1 alarm integrator (almi)................................................65 9.5 receive and transmit digital jitter attenuator (rjat, tjat) ...........................................................................................65 9.6 timing options (tops) ..........................................................72 9.7 pseudo random binary sequence generation and detection (prbs) ...................................................................73 9.8 pseudo random pattern generation and detection (prgd) ........................................................................................73 9.9 ds3 framer (ds3-frmr) ........................................................73
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, in c. and for its customers? internal use iii 9.10 performance monitor accum ulator (ds3-pmon) .....76 9.11 ds3 transmitter (ds3-tran) ..............................................76 9.12 m23 multiplexer (mx23)........................................................77 9.13 ds2 framer (ds2-frmr) ........................................................78 9.14 m12 multiplexer (mx12)........................................................80 9.15 tributary payload processor (vtpp) ...........................81 9.15.1 clock generator.......................................................81 9.15.2 incoming timing generator ...................................81 9.15.3 incoming multiframe detector ...........................82 9.15.4 pointer interpreter ................................................82 9.15.5 payload buffer...........................................................82 9.15.6 outgoing timing generator ..................................82 9.15.7 pointer generator ...................................................83 9.16 receive tributary path overhead processor (rtop) .....................................................................................................84 9.16.1 clock generator.......................................................84 9.16.2 timing generator ......................................................84 9.16.3 error monitor............................................................84 9.17 receive tributary demapper (rtdm)..............................86 9.18 parallel in to serial out converter (piso) ...............88 9.19 ds3 mapper drop side (d3md)............................................89 9.19.1 ds3 demapper ..............................................................90 9.19.2 ds3 demapper elastic store .................................91 9.19.3 ds3 desynchro nizer.................................................91
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use iv 9.20 transmit tributary path overhead processor (ttop)92 9.21 transmit remote alarm processor (trap) ................93 9.22 transmit tributary mapper (ttmp).................................94 9.23 serial in to parallel out converter (sipo) ...............95 9.24 ds3 mapper add side (d3ma) ...............................................95 9.24.1 ds3 mapper serializer .............................................96 9.24.2 ds3 mapper elastic store ......................................96 9.24.3 ds3 synchroni zer......................................................96 9.25 egress system interface (esif) ......................................97 9.26 ingress system interface (isif) ......................................98 9.27 extract scaleable bandwidth interconnect (exsbi) .....................................................................................................99 9.28 insert scaleable bandwidth interconnect (insbi)100 9.29 scaleable bandwidth interconnect piso (sbipiso)100 9.30 scaleable bandwidth interconnect sipo (sbisipo)101 9.31 jtag test access port......................................................101 9.32 microprocessor in terface ...........................................101 10 normal mode register description ......................................127 11 test features description .......................................................128 11.1 jtag test port .....................................................................136 11.1.1 boundary scan register ......................................137 12 operation.........................................................................................148 12.1 ds3 frame format...............................................................148 12.2 servicing interrupts .......................................................150
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use v 12.3 using the performance monitoring features.......150 12.4 t1/e1 framer loopback modes ......................................155 12.5 ds3 loopback modes .........................................................157 12.6 telecom bus mapper/demapper loopback modes .160 12.7 sbi bus data formats.........................................................161 12.8 serial clock and da ta format .......................................176 12.9 prgd pattern generation ...............................................176 12.10 jtag support........................................................................179 12.10.1 tap controller ...................................................181 13 functional ti ming .........................................................................188 13.1 ds3 line side interface timing .......................................188 13.2 ds3 system side interface timing ................................190 13.3 telecom drop bus interface timing ...........................191 13.4 telecom add bus inte rface timing ..............................194 13.5 sonet/sdh serial alarm port timing ...........................196 13.6 sbi drop bus interface timing .......................................198 13.7 sbi add bus interf ace timing ..........................................199 13.8 egress serial clock and data interface timing ....199 13.9 ingress serial clock and data interface timing ...200 14 absolute maximum ratings........................................................201 15 d.c. character istics....................................................................202 16 microprocessor interface timing characteristics......205 17 temap timing chara cteristics .................................................209 18 ordering and therma l information ......................................231
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use vi 19 mechanical info rmation.............................................................232 figures figure 1 - channelized ds3 circuit emulation application .......16 figure 2 - high density frame relay application ..........................16 figure 3 - temap block diagram ..........................................................18 figure 4 - vt/tu mapper block diagram ............................................19 figure 5 - ds3 framer only mode block diagram .........................20 figure 6 - pin diagram..............................................................................25 figure 7 - crc multiframe align ment algorithm ..........................61 figure 8 - djat jitter tolerance t1 modes......................................68 figure 9 - djat jitter tolerance e1 modes .....................................69 figure 10 - djat minimum jitter tolerance vs. xclk accuracy t1 modes 70 figure 11 - djat minimum jitter tolerance vs. xclk accuracy e1 modes 70 figure 12 - djat jitter transfer t1 modes ........................................71 figure 13 - djat jitter transfer e1 modes ........................................72 figure 14 - clock master: clear channel .........................................98 figure 15 - clock slave: clear channel.............................................98 figure 16 - clock master: clear channel .........................................99 figure 17: ds3 fr ame struct ure ........................................................148 figure 18 - fer count vs. ber (e1 mode) ............................................152 figure 19 - crce count vs. ber (e1 mode) .........................................153 figure 20 - fer count vs. ber (t1 esf mode) ....................................153
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use vii figure 21 - crce count vs. ber (t1 esf mode) .................................154 figure 22 - crce count vs. ber (t1 sf mode)....................................155 figure 23: t1/e1 line loopback.............................................................156 figure 24: t1/e1 diagnostic digital loopback................................157 figure 25: ds3 diagnostic loopback diagram ...............................158 figure 26: ds3 line loopback diagram..............................................159 figure 27: ds2 loopback diagram.......................................................159 figure 28: telecom diagnostic loopback diagram .....................160 figure 29: telecom line loopback diagram ...................................161 figure 30: prgd pa ttern generator .................................................176 figure 31: boundary sc an archite cture ........................................180 figure 32: tap controller finite state machine ..........................182 figure 33: input observation cell (in_cell) ...................................185 figure 34: output cell (out_cell) .....................................................186 figure 35: bidirectional cell (io_cell).............................................186 figure 36: layout of output enable and bidirectional cells 187 figure 37: receive bipolar ds3 stream............................................188 figure 38: receive unipolar ds3 stream .........................................188 figure 39: transmit bipolar ds3 stream .........................................189 figure 40: transmit unipolar ds3 stream.......................................189 figure 41: framer mode ds3 transmit input stream ..................190 figure 42: framer mode ds3 transmit input stream with tgapclk 190 figure 43: framer mode ds3 receive output stream.................191
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, in c. and for its customers? internal use viii figure 44: framer mode ds3 receive output stream with rgapclk 191 figure 45: telecom drop bus timing - sts-1 spes / au3 vcs........192 figure 46: telecom drop bus timing - locked sts-1 spes / au3 vcs 193 figure 47: telecom drop bus timing - au4 vc..................................194 figure 48: output bus timing - locked sts-1 spes / au3 vcs......195 figure 49 - output bus timing - lo cked au4 vc case.....................196 figure 50: remote serial alarm port timing..................................197 figure 51: sbi drop bus t1/e1 functional timing...........................198 figure 52: sbi drop bus ds 3 functional timing .............................198 figure 53: sbi add bus justification request functional timing 199 figure 54: t1 and e1 egress interface clock master: clear channel mode............................................................................................199 figure 55: t1 and e1 egress interface clock slave: clear channel mode............................................................................................200 figure 56: t1 and e1 ingress interface clock master: clear channel mode............................................................................................200 figure 57: ds3 transmit interface timing ....................................... 211 figure 58: ds3 receive interface timing..........................................214 figure 59: line side telecom bus inputtiming................................216 figure 60: telecom bus output timing .............................................217 figure 61: telecom bus tristate output timing ...........................217 figure 62: sbi add bus timing ................................................................219 figure 63: sbi drop bus timing .............................................................220 figure 64: sbi drop bus collision avoidance timing ...................221
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use ix figure 65: xclk input timing .................................................................222 figure 66: egress interface input timing - clock master : clear channel mode............................................................................................223 figure 67: egress interface input timing - clock slave : clear channel mode............................................................................................224 figure 68: ingress interface timi ng - clock master modes....225 figure 69: transmit line interface timing ......................................226 figure 70: remote serial alarm port timing..................................228 figure 71: jtag port interface timing..............................................230 figure 72: 324 pin pbga 23x23mm body................................................232 tables table 1 - e1-frmr framing states......................................................62 table 2 - path signal label mismatch state ..................................85 table 3 - asynchronous t1 tr ibutary mapping............................86 table 4 - asynchronous e1 tr ibutary mapping ...........................87 table 5 - desynchronizer clock generation algorithm ........89 table 6 - asynchronous ds3 mapping to sts-1 (stm-0/au3).......90 table 7 - ds3 ais format. .......................................................................90 table 8 - ds3 desynchronizer clock gapping algorithm. ......92 table 9 - ds3 synchronizer bit stuffing algorithm. ................97 table 10 - register memory map .......................................................102 table 11 - instruction re gister........................................................136 table 12 - identification register ....................................................137 table 13 - boundary scan chain ........................................................137
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use x table 14 - pmon counter saturation limits (e1 mode) ..............151 table 15 - pmon counter saturation limits (t1 mode)...............151 table 16 - structure for carrying multiplexed links ............163 table 17 ? t1/tvt1.5 tributary column numbering......................163 table 18 - e1/tvt2 tributary column numbering .........................164 table 19: sbi t1/e1 link rate information.........................................165 table 20: sbi t1/e1 clock rate encoding ..........................................166 table 21: ds3 link rate information ..................................................166 table 22: ds3 clock rate encoding ...................................................167 table 23 - t1 framing format ..............................................................168 table 24 ? e1 framing format .............................................................169 table 25 - ds3 framing format ...........................................................171 table 26 - ds3 block format ...............................................................172 table 27 - ds3 multi-frame stuffing format.................................172 table 28 - transparent vt1.5/tu11 format .....................................173 table 29 ? transparent vt2/tu12 format .......................................175 table 30: pseudo random pattern generation (ps bit = 0)........178 table 31: repetitive pattern generation (ps bit = 1)...................179 table 32 - absolute maximum ratings..............................................201 table 33 - d.c. charact eristics .........................................................202 table 34: microprocessor inte rface read access ....................205 table 35: microprocessor interface write access ..................207 table 36: rtsb timing ...............................................................................209 table 37: ds3 transmit interface timing..........................................209
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use xi table 38: ds3 receive interface timing ............................................213 table 39: line side telecom bus input timing (figure 62) ...........215 table 40 ? telecom bus output timing (figure 63 to figure 64)216 table 41: sbi add bus timing (figure 62) ............................................218 table 42 ? sbi drop bus timing (figure 63 to figure 64) ..............219 table 43: xclk input (figure 65) ...........................................................222 table 44: egress interface input timing - clock master : clear channel mode (figure 66)......................................................................223 table 45: egress interface input timing - clock slave : clear channel mode (figure 67)......................................................................224 table 46: ingress interface timing - clock master modes (figure 68)....................................................................................................225 table 47: transmit line interface timing (figure 69)...................226 table 48: remote serial alarm port timing ....................................227 table 49: jtag port interface .............................................................229 table 50 - ordering and ther mal information ............................231 table 51 - thermal information ? theta ja vs. airflow.............231
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 1 1 features integrates a sonet/sdh vt1.5/vt2/tu11/tu12 bit asynchronous mapper, a full featured m13 multiplexer with ds3 framer, and a sonet/sdh ds3 mapper in a single monolithic device for terminating ds3 multiplexed t1 streams, sonet/sdh mapped t1 streams or sonet/sdh mapped e1 streams. five fundamental modes of operation: single sts-1, au3 or tug3 bit asynchronous vt1.5 or tu-11 mapper with ingress or egress per tributary link monitoring for 28 t1s. ds3 m13 multiplexer with ingress or egress per link monitoring for 28 t1s. up to 28 ds3 multiplexed t1 streams are mapped as bit asynchronous vt1.5 virtual tributaries or tu-11 tributary units, providing a transmultiplexing (?transmux?) function between ds3 and sonet/sdh with ingress or egress per tributary link monitoring for 28 t1s. single sts-1, au3 or tug3 bit asynchronous vt2 or tu-12 mapper with ingress or egress per tributary link monitoring for 21 e1s or 21 t1s. up to 21 e1 streams multiplexed into a ds3 following the itu-t g.747 recommendation. this e1 mode of operation is restricted to using the serial clock and data system interfaces. up to 28 vt1.5/tu11 or 21 vt2/tu12 tributaries can be passed between the line sonet/sdh bus and the sbi bus as transparent virtual tributaries with pointer processing. when adding and dropping t1 or e1 tributaries the mapper and demapper blocks allow for up to 28 vt1.5/tu11 or 21 vt2/tu12 tributaries to be processed from any tributary location within the full sts-3/stm-1. on the telecom drop bus side this requires that the sts-3/stm-1 be in locked mode such that the j1 bytes immediately follow the c1 bytes. supports a byte serial scaleable bandwidth interconnect (sbi) bus interface for high density system side device interconnection of up to 84 t1 streams, 63 e1 streams or 3 ds3 streams. this interface also supports transparent virtual tributaries when used with the sonet/sdh mapper. provides jitter attenuation in the t1 or e1 receive and transmit directions.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 2 provides two independent de-jittered t1 or e1 re covered clocks for system timing and redundancy. provides an on-board programmable binary sequence generator and detector for error testing at ds3 rates. includes support for patterns recommended in itu-t o.151. also provides prbs generators and detectors on each tributary for error testing at ds1, e1 and nxds0 rates as recommended in itu-t o.151 and o.152. supports the m23 and c-bit parity ds3 formats. standalone unchannelized ds3 framer mode for access to the entire ds3 payload. when configured to operate as a ds3 framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits. ds3 transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed). provides a sonet/sdh add/drop bus interface with integrated vt1.5, tu- 11, vt2 and tu-12 mapper for t1and e1 streams. also provides a ds3 mapper. register level compatibility with the pm8315 temux, the pm4388 toctl octal t1 framer, the pm6388 eoctl octal e1 framer, the pm4351 comet e1/t1 transceiver and the pm8313 d3mx m13 multiplexer/demultiplexer. provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. low power 2.5v/3.3v cmos technology. all pins are 5v tolerant. 324-pin fine pitch pbga package (23mm x 23mm). supports industrial temperature range (-40 o c to 85 o c) operation. each one of 28 t1 perfo rmance monitoring sections: frames to ds-1 signals in sf and esf formats.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 3 frames to ttc jt-g.704 multiframe formatted j1 signals. supports the alternate crc-6 calc ulation for japanese applications. accepts gapped data streams to support higher rate demultiplexing. provides red, yellow, and ais alarm integration. provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. a pseudo-random sequence user selectable from 2 11 ?1, 2 15 ?1 or2 20 ?1, may be detected in the t1 stream in either the ingress or egress directions. the detector counts pattern errors using a 24-bit non-saturating prbs error counter. the pseudo-random sequence can be the entire t1 or any combination of ds0s within a framed t1. line side interface is either from the ds3 interface via the m13 multiplex or from the sonet/sdh drop bus via the vt1.5, tu-11, vt2 or tu-12 demapper. system side interface is either serial clock and data or sbi bus. frames in the presence of and detects the ?japanese yellow? alarm. provides external access for up to two de-jittered recovered t1 clocks. each one of 21 e1 perfo rmance monitoring sections: frames to itu-t g.704 basic and crc-4 mu ltiframe formatted e1 signals. the framing procedures are consis tent itu-t g.706 specifications. provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. a pseudo-random sequence user selectable from 2 11 ?1, 2 15 ?1 or2 20 ?1, may be detected in the e1 stream in either the ingress or egress directions. the detector counts pattern errors using a 24-bit non-saturating prbs error counter. the pseudo-random sequence can be the entire e1 or any combination of timeslots within the framed e1.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 4 line side interface is from the sonet/sdh drop bus via the vt2 or tu-12 demapper. system side interface is either serial clock and data or sbi bus. provides external access for up to two de-jittered recovered e1 clocks. sonet/sdh tributary path processing section: interfaces with a byte wide telecom add/drop bus, interfacing directly with the pm5362 tupp-plus and pm5342 spectra-155. compensates for pleisiochronous relationships between incoming and outgoing higher level (sts-1, au4, au3) synchronous payload envelope frame rates through processing of the lower level tributary pointers. optionally frames to the h4 byte in the path overhead to determine tributary multi-frame boundaries and generates change of loss-of-frame status interrupts. detects loss of pointer (lop) and re-acquisition for each tributary and optionally generates interrupts. detects tributary path alarm indication signal (ais) and return to normal state for each tributary and optionally generates interrupts detects tributary elastic store underflow and overflow and optionally generates interrupts. provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (pslm) and return to matched state for each tributary and optionally generates interrupts. detects tributary path signal label unstable alarms (pslu) and return to stable state for each tributary and optionally generates interrupts. detects assertion and removal of tributary extended remote defect indications (rdi) for each tributary and optionally generates interrupts. calculates and compares the tributary path bip-2 error detection code for each tributary and configurable to accumulate the bip-2 errors on block or bit basis in internal registers. allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under sw control.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 5 allows sw to force the ais insertion on a per tributary basis. inserts valid h4 byte and all-zeros fixed stuff bytes. remaining path overhead bytes (j1, b3, c2,g1, f2, z3, z4 , z5) are set to all-zeros. inserts valid pointers and all-zeros transport overhead bytes on the outgoing telecom add bus, with valid control signals. support in-band error reporti ng by updating the febe, rdi and auxiliary rdi bits in the v5 byte with the status of the incoming stream and remote alarm pins. calculates and inserts the tributary path bip-2 error detection code for each tributary. sonet/sdh vt/tu mapper section: inserts up to 28 bit asynchronous mapped vt1.5 virtual tributaries into an sts-1 spe from t1 streams. inserts up to 28 bit asynchronous mapped tu-11 tributary units into a stm- 1/vc4 tug3 or stm-1/vc3 from t1 streams. inserts up to 21 bit asynchronous mapped vt2 virtual tributaries into an sts- 1 spe from e1 streams. inserts up to 21 bit asynchronous mapped tu-12 tributary units into an stm- 1/vc4 tug3 or stm-1/vc3 from e1 or t1 streams. bit asynchronous mapping assigns stuff control bits for all streams independently using an all digital control loop. stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer. sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control extracts up to 28 bit asynchronous mapped vt1.5 virtual tributaries from an sts-1 spe into t1 streams via an optional elastic store. extracts up to 28 bit asynchronous mapped tu-11 tributary units from an stm-1/vc4 tug3 or stm-1/vc3 into t1 streams via an optional elastic store. extracts up to 21 bit asynchronous mapped vt2 virtual tributaries from an sts-1 spe into e1 streams via an optional elastic store.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 6 extracts up to 21 bit asynchronous mapped tu-12 tributary units from an stm-1/vc4 tug3 or stm-1/vc3 into e1 or t1 streams via an optional elastic store. demapper ignores all transport overhead bytes, path overhead bytes and stuff (r) bits performs majority vote c-bit decoding to detect stuff requests. sonet/sdh ds3 mapper section: maps a ds3 stream into an sts-1 spe (au3). sets all fixed stuff (r) bits to zeros or ones per microprocessor control extracts a ds3 stream from an sts-1 spe (au3). demapper ignores all transport overhead bytes, path overhead bytes and stuff (r) bits performs majority vote c-bit decoding to detect stuff requests complies with ds3 to sts-1 asynchronous mapping standards ds3 receiver section: frames to a ds3 signal with a maximum average reframe time of less than 1.5 ms (as required by tr-tsy-000009 section 4.1.2 and tr-tsy-000191 section 5.2). decodes a b3zs-encoded signal and indicates line code violations. the definition of line code violation is software selectable. provides indication of m-frame boundaries from which m-subframe boundaries and overhead bit positions in the ds3 stream can be determined by external processing. detects the ds3 alarm indication signal (ais) and idle signal. detection algorithms operate correctly in the presence of a 10 -3 bit error rate. accumulates up to 65,535 line code violation (lcv) events per second, 65,535 p-bit parity error events per second, 1023 f-bit or m-bit (framing bit) events per second, 65,535 excessive zero (exz) events per second, and when enabled for c-bit parity mode operation, up to 16,383 c-bit parity error
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 7 events per second, and 16,383 far end block error (febe) events per second. detects and validates bit-oriented codes in the c-bit parity far end alarm and control channel. terminates the c-bit parity path maintenance data link with an integral hdlc receiver having a 128-byte deep fifo buffer with programmable interrupt threshold. supports polled or interrupt-driven operation. selectable none, one or two address match detection on first byte of received packet. programmable pseudo-random test-sequence detection?(up to 2 32 -1 bit length patterns conforming to itu-t o.151 standards) and analysis features. ds3 transmit section: provides the overhead bit insertion for a ds3 stream. provides a bit serial clock and data interface, and allows the m-frame boundary and/or the overhead bit positions to be located via an external interface provides b3zs encoding. generates an b3zs encoded 100? repeating pattern to aid in pulse mask testing. inserts far end receive failure (ferf), the ds3 alarm indication signal (ais) and the idle signal when enabled by internal register bits. provides optional automatic insertion of far end receive failure (ferf) on detection of loss of signal (los), out of frame (oof), alarm indication signal (ais) or red alarm condition. provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the c-bit parity application, c-bit parity error events, and far end block error (febe) events. supports insertion of bit-oriented codes in the c-bit parity far end alarm and control channel. optionally inserts the c-bit parity path maintenance data link with an integral hdlc transmitter. supports polled and interrupt-driven operation.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 8 provides programmable pseudo-random test sequence generation (up to 2 32 -1 bit length sequences conforming to itu-t o.151 standards) or any repeating pattern up to 32 bits. the test pattern can be framed or unframed. diagnostic abilities include single bit erro r insertion or erro r insertion at bit error rates ranging from 10 -1 to 10 -7 . m23 multiplexer section: multiplexes 7 ds2 bit streams into a single m23 format ds3 bit stream. performs required bit stuffing/destuffing including generation and interpretation of c-bits. includes required fifo buffers for rate adaptation in the multiplex path. allows insertion and detection of per ds2 payload loopback requests encoded in the c-bits to be activated under microprocessor control. internally generates ds2 clock for use in integrated m13 or c-bit parity multiplex applications. alternatively accepts external ds2 clock reference. allows per ds2 alarm indication signal (ais) to be activated or cleared for either direction under microprocessor control. allows ds2 alarm indication signal (ais) to be activated or cleared in the demultiplex direction automatically upon loss of ds3 frame alignment or signal. supports c-bit parity ds3 format. ds2 framer section: frames to a ds2 (ansi t1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by tr-tsy-000009 section 4.1.2 and tr-tsy-000191 section 5.2). detects the ds2 alarm indication signal (ais) in 9.9 ms in the presence of a 10 -3 bit error rate. extracts the ds2 x-bit remote alarm indication (rai) bit and indicates far end receive failure (ferf). accumulates up to 255 ds2 m-bit or f-bit error events per second.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 9 ds2 transmitter section: generates the required x, f, and m bits into the transmitted ds2 bit stream. allows inversion of inserted f or m bits for diagnostic purposes. provides for transmission of far end receive failure (ferf) and alarm indication signal (ais) under microprocessor control. provides optional automatic insertion of far end receive failure (ferf) on detection of out of frame (oof), alarm indication signal (ais) or red alarm condition. m12 multiplexer section: multiplexes four ds1 bit streams into a single m12 format ds2 bit stream. performs required bit stuffing including generation and interpretation of c- bits. includes required fifo buffers for rate adaptation in the multiplex path. performs required inversion of second and fourth multiplexed ds1 streams as required by ansi t1.107 section 7.2. allows insertion and detection of per ds1 payload loopback requests encoded in the c-bits to be activated under microprocessor control. allows per tributary alarm indication signal (ais) to be activated or cleared for either direction under microprocessor control. allows automatic tributary ais to be activated upon ds2 out of frame. scaleable bandwidth interconnect (sbi) bus: provides a high density byte serial interconnect for all framed and unframed temap links. utilizes an add/drop configuration to asynchronously mutliplex up to 84 t1s, 63 e1s or 3 ds3s, equivalent to three temaps, with multiple payload or link layer processors. external devices can access unframed ds3, framed unchannelized ds3, unframed (clear channel) t1s, unframed (clear channel) e1s, transparent virtual tributaries or transparent tributary units over this interface.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 10 transparent vt/tu access can be selected only when tributaries are mapped into sonet/sdh. transparent vt1.5s and tu-11s can be selected on a per tributary basis in combination with framed and unframed t1s. transparent vt2s and tu-12s can be selected on a per tributary basis in combination with framed and unframed e1s. transmit timing is mastered either by the temap or a layer 2 device connecting to the sbi bus. timing mastership is selectable on a per tributary basis, where a tributary is either an individual t1, e1 or a ds3.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 11 2 applications sonet/sdh add drop multiplexers sonet/sdh terminal multiplexers m23 based m13 multiplexer c-bit parity based m13 multiplexer channelized and unchannelized ds3 frame relay interfaces
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 12 3 references american national standard for telecommunications - digital hierarchy - synchronous ds3 format specifications, ansi t1.103-1993 american national standard for telecommunications ? ansi t1.105 ? ?synchronous optical network (sonet) ? basic description including multiplex structure, rates, and formats,? october 27, 1995. american national standard for telecommunications ? ansi t1.105.02 ? ?synchronous optical network (sonet) ? payload mappings,? october 27, 1995. american national standard for telecommunications - digital hierarchy - formats specification, ansi t1.107-1995 american national standard for telecommunications - digital hierarchy - layer 1 in-service digital transmission performance monitoring, ansi t1.231-1997 american national standard for telecommunications - carrier to customer installation - ds-1 meta llic interface specification, ansi t1.403-1995 american national standard for telecommunications - customer installation?to- network - ds3 metallic interface specification, ansi t1.404-1994 american national standard for telecom?unications - integrated services digital network (isdn) primary rate- customer installation metallic interfaces layer 1 specification, ansi t1.408-1990 bell communications research, tr?tsy-000009 - asynchronous digital multiplexes requirements and objectives, issue 1, may 1986 bell communications research - ds-1 rate digital service monitoring unit functional specification, ta-tsy-000147, issue 1, october, 1987 bell communications research - alarm indication signal requirements and objectives, tr-tsy-000191 issue 1, may 1986 bell communications research - wideband and broadband digital cross- connect systems generic criteria, tr-nwt-000233, issue 3, november 1993 bellcore gr-253-core ? ?sonet transport systems: common criteria,? issue 2, revision 1, december 1997.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 13 bell communications research - integrated digital loop carrier generic requirements, objectives, and interface, tr-nwt-000303, issue 2, december, 1992 bell communications research - transport systems generic requirements (tsgr): common requirement, tr-tsy-000499, issue 5, december, 1993 bell communications research - otgr: network maintenance transport surveillance - generic digital trans mission surveillance, tr-tsy-000820, section 5.1, issue 1, june 1990 at&t - requirements for interfacing digital terminal equipment to services employing the extended superframe format, tr 54016, september, 1989. at&t - accunet t1.5 - service description and interface specification, tr 62411, december, 1990 itu study group xviii ? report r 105, geneva, 9-19 june 1992 etsi - ets 300 011 - isdn primary rate user-network interface specification and test principles, 1992. etsi - ets 300 233 - access digital section for isdn primary rates, may 1994 etsi - ets 300 324-1 - signaling protocols and switching (sps); v interfaces at the digital local exchange (le) v5.1 interface for the support of access network (an) part 1: v5.1 interface specification, february, 1994. etsi - ets 300 347-1 - signaling protocols and switching (sps); v interfaces at the digital local exchange (le) v5.2 interface for the support of access network (an) part 1: v5.2 interface specification, september 1994. etsi ets 300 417-1-1 ? ?transmission and multiplexing (tm); generic functional requirements for synchronous digital hierarchy (sdh) equipment; part 1-1: generic processes and performance,? january, 1996. etsi, generic functional requirements for synchronous digital hierarchy (sdh) equipment, jan 1996 itu-t - recommendation g.704 - synchronous frame structures used at primary hierarchical levels, july 1995. itu-t - recommendation g.706 - fr ame alignment and crc procedures relating to g.704 frame structures, 1991.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 14 itu-t - recommendation g.732 ? characteristics of primary pcm multiplex equipment operating at 2048 kbit/s, 1993. itu-t recommendation g.707 ? network node interface for the synchronous digital hierarchy, 1996 itu-t recommendation g.747 ? second order digital multiplex equipment operating at 6312kbit/s and multiplexing three tributaries at 2048 kbit/s, 1988 itu-t recommendation g.775, - loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria, 11/94 itu-t recommendation g.783 ? ?characteristics of synchronous digital hierarchy (sdh) equipment f unctional blocks,? april, 1997. itu-t recommendation g.823, - the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 03/94 itu-t recommendation g.964, - v-interfaces at the digital local ex?hange (le) - v5.1 interface (based on 2048 kbit/s) for the support of access network (an), june 1994. itu-t recommendation g.965, - v-interfaces at the digital local ex?hange (le) - v5.2 interface (based on 2048 kbit/s) for the support of access network (an), march ?995. itu-t - recommend?tion i.431 - primary rate user-network interface ? layer 1 specification, 1993. itu-t recommendation o.151 ? error performance measuring equipment operating at the primary rate and above, october 1992 itu-t recommendation o.152 ? error performance measuring equipment for bit rates of 64 kbit/s and n x 64 kbit/s, october 1992 itu-t recommendation o.153 - basic parameters for the measurement of error performance at bit rates below the primary rate, october 1992. itu-t recommendation q.921 - isdn user-network interface data link layer specification, march 1993 international organization for standardization, iso 3309:1984 - high-level data link control procedures - frame structure
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 15 pmc-sierra inc., pmc-1980577 ? saturn compatible scaleable bandwidth interface (sbi) specification, issue 3, 1998 ttc standard jt-g704 - frame structures on primary and secondary hierarchical digital interfaces, 1995. ttc standard jt-g706 - frame sy nchronization and crc procedure ttc standard jt-i431 - isdn primary rate user-network interface layer 1 - specification, 1995. nippon telegraph and telephone corporation - technical reference for high- speed digital leased circuit services, third edition, 1990.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 16 4 application examples figure 1 - channelized ds3 ci rcuit emulation application ds3 liu ds3 liu ds3 liu pm5365 temap 28 t1/21 e1 pmon m13 mux, ds3 framer pm5365 temap 28 t1/21 e1 pmon m13 mux, ds3 framer pm5365 temap 28 t1/21 e1 pmon m13 mux, ds3 framer pm73122 aal1gator-32 atm sar pm73122 aal1gator-32 atm sar pm73122 aal1gator-32 atm sar sbi bus utopia bus figure 2 - high density frame relay application pm5342 spectra 155 payload extractor/ aligner high density t1/e1 frame relay port card pm5365 temap #1 in vt1.5 or vt2.0 mapper mode mapper and telecom bus i/f t1 pmon #28 or e1 pmon #21 t1 or e1 pmon #1 ? pm5365 temap #2 pm5365 temap #3 sbi bus pci bus pm7384 freedm 84p672 high density hdlc controller sts-3/ stm-1
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 17 5 block diagram 5.1 top level block diagram figure 3 shows the complete temap. clear channel t1 links can be multiplexed into the ds3 or can be mapped into the telecom bus as sonet vt1.5 virtual tributaries or as sdh tu-11 or tu-12 tributary units, shown at the bottom of the diagram. clear channel e1 links can be mapped into the telecom bus as sonet vt2 virtual tributaries or as sdh tu-12 tributary units, shown at the bottom of the diagram. system side access to the t1s and e1s is available as serial clock and data or the sbi bus. ds3 line side access is via the clock and data interface for line interface units or ds3 mapped into the sonet/sdh telecom bus. unchannelized ds3 system side access is available through a serial clock and data interface or the sbi bus, both shown at the top of the diagram.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 18 figure 3 - temap block diagram a l m i a l a r m i n t e g r a t o r t 1 / e 1 - f r m r f r a m e a l i g n m e n t , a l a r m e x t r a c t i o n r j a t d i g i t a l j i t t e r a t t e n u a t o r t j a t d i g i t a l j i t t e r a t t e n u a t o r t o p s t i m i n g o p t i o n s x c l k a [ 1 3 : 0 ] d [ 7 : 0 ] r d b w r b c s b a l e i n t b r s t b m p i f m i c r o - p r o c e s s o r i n t e r f a c e i d [ 1 : 2 8 ] i c l k [ 1 : 2 8 ] e d [ 1 : 2 8 ] c t c l k e c l k [ 1 : 2 8 ] j t a g t e s t a c c e s s p o r t t d o t d i t c l k t m s t r s t b t c l k t p o s / t d a t t n e g / t m f p r c l k r p o s / r d a t r n e g / r l c v t r a n d s 3 t r a n s m i t f r a m e r f r m r d s 3 r e c e i v e f r a m e r b 3 z s e n c o d e b 3 z s d e c o d e o n e o f 2 8 t 1 o r 2 1 e 1 p e r f o r m a n c e m o n i t o r i n g f r a m e r s e x s b i s b i e g r e s s b u s s a d a t a [ 7 : 0 ] s a d p s a p l s a v 5 s d d a t a [ 7 : 0 ] s d d p s d p l s d v 5 t i c l k v t p p v t / t u p a y l o a d p r o c e s s o r l a d a t a [ 7 : 0 ] l a d p l a p l l a c 1 j 1 v 1 l a o e l a c 1 l r e f c l k l d d a t a [ 7 : 0 ] l d c 1 j 1 l d d p l d p l l d t p l l d v 5 l d a i s r g a p c l k / r s c l k r d a t o r f p o / r m f p o r o v r h d t f p o / t m f p o / t g a p c l k t d a t i t f p i / t m f p i m x 2 3 m 2 3 m u x / d e m u x f r m r d s 2 f r a m e r # 1 o n e o f s e v e n f r m r / m 1 2 s d e m u x m x 1 2 m 1 2 m u x / r a d e a s t r a d e a s l c k r a d e a s t f p r a d w e s t r a d w e s t c k r a d w e s t f p r t o p r e c e i v e t r i b u t a r y p a t h o / h p r o c e s s o r r t d m r e c e i v e t r i b u t a r y d e m a p p e r d 3 m d d s 3 d r o p s i d e m a p p e r v t p p t r a n s m i t v t / t u p a y l o a d p r o c e s s o r r b o c r x f e a c r d l c r x h d l c p m o n p e r f . m o n i t o r d 3 m a d s 3 a d d s i d e m a p p e r t t m p t r a n s m i t t r i b u t a r y m a p p e r s a j u s t _ r e q i n s b i s b i i n g r e s s b u s s r e f c l k s c 1 f p p i s o d e m a p p e r p a r a l l e l t o s e r i a l c o n v e r t e r s i p o s e r i a l t o p a r a l l e l c o n v e r t e r e s i f e g r e s s s y s t e m i n t e r f a c e i s i f i n g r e s s s y s t e m i n t e r f a c e r e c v c l k 1 r e c v c l k 2 c l k 5 2 m t t o p t r a n s m i t t r i b u t a r y p a t h o / h p r o c e s s o r p r b s p a t t e r n g e n e r - a t o r / d e t e c t o r s b i s i p o s e r i a l t o p a r a l l e l s b i p i s o p a r a l l e l t o s e r i a l s b i b a c t [ 1 : 0 ] s b i a c t t d p r t x h d l c x b o c t x f e a c t r a p t r a n s m i t r e m o t e a l a r m p r o c e s s o r p m o n p e r f o r m a n c e m o n i t o r c o u n t e r s
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 19 5.2 vt/tu mapper only mode block diagram figure 4 shows the temap configured as a vt or tu mapper. in this mode the temap provides access for up to 28 independent unframed 1.544mb/s streams or 21 independent unframed 2.048mb/s streams. the 1.544mb/s and 2.048mb/s streams can be accessed on the system side as clock and data as shown in figure 4, or they can be accessed via the sbi bus. the t1 or e1 framers and performance monitoring blo cks can be used to monitor the passing traffic in either the ingress or egress direction. the m13 multiplexer mode operates in much the same way as the vt and tu mapper shown in figure 4. figure 4 - vt/tu mapper block diagram rjat digital jitter attenuator tjat digital jitter attenuator xclk id[1:28] iclk[1:28] ed[1:28] eclk[1:28] one of 28 t1 or 21 e1 framers vtpp vt payload processor rtop receive tributary path o/h processor rtdm receive tributary demapper trap/ ttop transmit remote alarm & tributary patho/h processors ttmp transmit tributary mapper piso parallel to serial converter sipo serial to parallel converter recvclk1 recvclk2 almi alarm integrator pmon performance monitor counters t1/e1-frmr framer: frame alignment, alarm extraction vtpp vt payload processor ladata[7:0] ladp lapl lac1j1v1 laoe lac1 lrefclk lddata[7:0] ldc1j1 lddp ldpl ldtpl ldv5 ldais radeast radeaslck radeastfp radw est radw estck radw estfp
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 20 5.3 ds3 framer only block diagram figure 5 shows the temap configured as a ds3 framer. in this mode the temap provides access to the full ds3 unchannelized payload. the payload access (right side of diagram) has two clock and data interfacing modes, one utilizing a gapped clock to mask out the ds3 overhead bits and the second utilizing an ungapped clock with overhead i ndications on a separate overhead signal. the sbi bus can also be used to provide access to the unchannelized ds3. figure 5 - ds3 framer only mode block diagram tclk tpos/tdat tneg/tmfp rclk rpos/rdat rneg/rlcv tdati tfpi/tmfpi rdato rfpo/rmfpo rovrhd tran ds3 transmit framer frmr ds3 receive framer b3zs encode b3zs decode pmon perf. monitor rdlc rx hdlc tdpr tx hdlc tfpo/tmfpo/tgapclk rgapclk/rsclk ticlk
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 21 6 description the pm5365 vt/tu mapper and m13 multiplexer (temap) is a feature-rich device for use in any applications requiring high density link termination over t1 channelized ds3 or t1 and e1 channelized sonet/sdh facilities. the temap supports asynchronous multiplexing and demultiplexing of 28 ds1s into a ds3 signal as specified by ansi t1.107 and bell communications research tr-tsy-000009. it supports bit asynchronous mapping and demapping of 28 t1s or 21 e1s into sonet/sdh as specified by ansi t1.105, bell communications research gr-253-core and itu-t recommendation g.707. the temap also supports mapping of 21 t1s into sdh via tu-12s. up to 28 transparent vt1.5s and tu-11s or 21 transparent vt2s and tu-12s can be transferred between the sonet/sdh interface and the sbi bus interface. performance monitoring in either the ingress or egress direction for up to 28 t1s or 21 e1s in both sonet/sdh vt/tu mapper and m13 multiplexer modes. each t1 performance monitor detects and indicates the presence of yellow and ais patterns and also integrates yellow, red, and ais alarms. t1 performance monitoring with accumulation of crc-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. each e1 framer detects and indicates the presence of remote alarm and ais patterns and also integrates red and ais alarms. the e1 framers support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of crc multiframe. the e1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal. e1 performance monitoring with accu mulation of crc-4 errors, far end block errors and framing bit errors is provided. this device can also be configured as a ds3 framer, providing external access to the full ds3 payload, or a vt/tu mapper, providing access to unframed 1.544mb/s and 2.048mb/s links. prbs generation or detection is supported on a per t1 or e1 link basis. the temap can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. two low jitter recovered t1 clocks can be routed out side the temap for network timing applications.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 22 serial pcm interfaces to each t1 framer allow 1.544 mbit/s ingress/egress system interfaces to be directly supported. a scaleable bandwidth interconnect (sbi) high density byte serial system interface provides higher levels of integration and dense interconnect. the sbi bus interconnects up to 84 t1s or 63 e1. the sbi allows transmit timing to be mastered by either the temap or link layer device connected to the sbi bus. this interconnect allows up to 3 temaps to be connected in parallel to provide the full complement of 84 t1s or 63 e1s of traffic. in addition to clear channel t1s and e1s the temap can transport framed or unframed ds3 links over the sbi bus. when configured as a ds3 multiplexer/demultiplexer or ds3 framer, the temap accepts and outputs either or both digital b3zs-encoded bipolar and unipolar signals compatible with m23 and c-bit parity applications. in the ds3 receive direction, the temap frames to ds3 signals with a maximum average reframe time of 1.5 ms in the presence of 10 -3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, c-bit parity errors, far end block errors, ais, far end receive failure and idle code. the ds3 framer is an off-line framer, indicating both out of frame (oof) and change of frame alignment (cofa) events. the error events (c-bit, febe, etc.) are still indicated while the framer is oof, based on the previous frame alignment. when in c-bit parity mode, the path maintenance data link and the far end alarm and control (feac) channels are extracted. hdlc receivers are provided for path maintenance data link support. in addition, valid bit-oriented codes in the feac channels are detected and are available through the microprocessor port. error event accumulation is also provided by the temap. framing bit errors, line code violations, excessive zeros occurrences, parity errors, c-bit parity errors, and far end block errors are accumulated. error accumulation continues even while the off-line framers are indicating oof. the counters are intended to be polled once per second, and are sized so as not to saturate at a 10 -3 bit error rate. transfer of count values to holding registers is initiated through the microprocessor interface. in the ds3 transmit direction, the temap inserts ds3 framing, x and p bits. when enabled for c-bit parity operation, bit-oriented code transmitters and hdlc transmitters are provided for insertion of the feac channels and the path maintenance data links into the appropriate overhead bits. alarm indication signals, far end receive failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. when m23 operation is selected, the c-bit parity id bit (the first c-bit of the first m sub-frame) is forced to toggle so that downstream equipment will not confuse an m23-formatted stream with stuck-at-1 c-bits for c-bit parity
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 23 application. transmit timing is from an external reference or from the receive direction clock. the temap also supports diagnostic options which allow it to insert a pseudo random binary sequence (prbs) into a ds3 payload and checked in the receive ds3 payload for bit errors. a fixed 100100? pattern is available for insertion directly into the b3zs encoder for proper pulse mask shape verification. when configured in ds3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of the ds3 signal. bit stuffing and rate adaptation is performed. the c-bits are set appropriately, with the option of inserting ds2 loopback requests. interrupts can be generated upon detection of loopback requests in the received ds3. ais may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. c-bit parity is supported by generating a 6.3062723 mhz clock, which corresponds to a stuffing ratio of 100%. framing to the demultiplexed 6312 kbit/s data streams supports ds2 (ansi ti.107) frame formats. the maximum average reframe time is 7ms for ds2. far end receive failure is detected and m-bit and f-bit errors are accumulated. the ds2 framer is an off-line framer, indicating both oof and cofa events. error events (ferf, merr, ferr, perr, rai, framing word errors) are still indicated while the ds2 framer is indicating oof, based on the previous alignment. each of the seven 6312 kbit/s multiplexers may be independently configured to multiplex and demultiplex four 1544 kbit/s ds1s into and out of a ds2 formatted signal. tributary frequency deviations are accommodated using internal fifos and bit stuffing. the c-bits are set appropriately, with the option of inserting ds1 loopback requests. interrupts can be generated upon detection of loopback requests in the received ds2. ais may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. when configured as a ds3 framer the unchannelized payload of the ds3 link is available to an external device. the sonet/sdh line side interface provides sts-1 spe synchronous payload envelope processing and generation, tug3 tributary unit group processing and generation within a vc4 virtual container and vc3 virtual container processing and generation. the payload processor aligns and monitors the performance of sonet virtual tributaries (vts) or sdh tributary units (tus). maintenance functions per tributary include detection of loss of pointer, ais alarm, tributary path signal label mismatch and tributary path signal label unstable alarms. optionally interrupts can be generated due to the assertion and removal of any of the above alarms. counts are accumulated for tributary path bip-2 errors on a block or bit basis and for febe indications. the synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 24 path bip-2. the generator also inserts febe, rdi and enhanced rdi in the v5 byte. software can force ais insertion on a per tributary basis. a sonet/sdh mapper maps and demaps up to 28 t1s, 21 e1s or a single ds3 into a sts-1 spe, tug3 or vc3 through an elastic store. the fixed stuff (r) bits are all set to zeros or ones under microprocessor control. the bit asynchronous demapper performs majority vote c-bit decoding to detect stuff requests for t1, e1 and ds3 asynchronous mappings. the vt1.5/vt2/tu-11/tu-12 mapper uses an elastic store and a jitter attenuator capability to minimize jitter introduced via bit stuffing. the temap is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. all sources of interrupts can be masked and acknowledged through the microprocessor interface.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 25 7 pin diagram the temap is currently planned to be packaged in a 324-pin pbga package having a body size of 23mm by 23mm and a ball pitch of 1.0 mm. the center 36 balls are not used as signal i/os and are thermal balls. pin names and locations are defined in the pin description table in section 8. mechanical information for this package is in the section 19. figure 6 - pin diagram 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h 324 pbga j vss vss vss vss vss vss k vss vss vss vss vss vss l vss vss vss vss vss vss m vss vss vss vss vss vss n vss vss vss vss vss vss p vss vss vss vss vss vss r t bottom view u v w y aa a b 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 26 8 pin description pin name type pin no. function ds3 line side interface rclk input w5 receive input clock (rclk). rclk provides the receive direction timing. rclk is a ds3, nominally a 44.736 mhz, 50% duty cycle clock input. rpos/rdat input y7 positive input pulse (rpos). rpos represents the positive pulses received on the b3zs-encoded ds3 when dual rail input format is selected. receive data input (rdat). rdat represents the nrz (unipolar) ds3 input data stream when single rail input format is selected. rpos and rdat are sampled on the rising edge of rclk by default and may be enabled to be sampled on the falling edge of rclk by setting the rfall bit in the ds3 master receive line options register. rneg/rlcv input a b6 negative input pulse (rneg). rneg represents the negative pulses received on the b3zs-encoded ds3 when dual rail input format is selected. line code violation (rlcv). rlcv represents receive line code violations when single rail input format is selected. rneg and rlcv are sampled on the rising edge of rclk by default and may be enabled to be sampled on the falling edge of rclk by setting the rfall bit in the ds3 master receive line options register. tclk output a a7 transmit clock (tclk). tclk provides timing for circuitry downstream of the ds3 transmitter of the temap. tclk is nominally a 44.736 mhz, 50% duty cycle clock.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 27 pin name type pin no. function tpos/tdat output a b7 transmit positive pulse (tpos). tpos represents the positive pulses transmitted on the b3zs-encoded ds3 line when dual-rail output format is selected. transmit data output (tdat). tdat represents the nrz (unipolar) ds3 output data stream when single rail output format is selected. tpos and tdat are updated on the falling edge of tclk by default but may be enabled to be updated on the rising edge of tclk by setting the trise bit in the ds3 master transmit line options register. tpos and tdat are updated on ticlk rather than tclk when the ticlk bit in the ds3 master transmit line options register is set. tneg/tmfp output w6 transmit negative pulse (tneg). tneg represents the negative pulses transmitted on the b3zs-encoded ds3 line when dual-rail output format is selected. transmit multiframe pulse (tmfp). this signal marks the transmit m-frame alignment when configured for single rail operation. tmfp indicates the position of overhead bits in the transmit transmission system stream, tdat. tmfp is high during the first bit (x1) of the multiframe. tneg and tmfp are updated on the falling edge of tclk by default but may be enabled to be updated on the rising edge of tclk by setting the trise bit in the ds3 master transmit line options register. tneg and tmfp are updated on ticlk rather than tclk when the ticlk bit in the ds3 master transmit line options register is set. ticlk input a a6 transmit input clock (ticlk). ticlk provides the transmit direction timing. ticlk is nominally a 44.736 mhz, 50% duty cycle clock. this clock is only required when using the ds3 transmitter, either with the ds3 line side interface or the ds3 mapper. when not used this clock input should be connected to ground.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 28 pin name type pin no. function xclk/vclk input e20 crystal clock input (xclk). this 24 times t1 or e1 clock provides timing for many of the t1 and e1 portions of temap. xclk is nominally a 37.056 mhz 32ppm, 50% duty cycle clock when configured for t1 modes and is nominally a 49.152 mhz 32ppm, 50% duty cycle clock when configured for e1 modes. this clock is required for all operating modes of the temap. test vector clock (vclk). this signal is used during production testing.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 29 pin name type pin no. function ds3 system side interface rgapclk/rsclk output y3 framer recovered gapped clock (rgapclk). rgapclk is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register and the rxgapen bit in the ds3 master unchannelized interface options register. rgapclk is the recovered clock and timing reference for rdato. rgapclk is held either high or low during bit positions which correspond to overhead. framer recovered clock (rsclk). rsclk is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register. rsclk is the recovered clock and timing reference for rdato, rfpo/rmfpo, and rovrhd. this signal shares a signal pin with iclk[1]. when enabled for unchannelized ds3 operation this signal will be rgapclk/rsclk, otherwise it will be iclk[1]. rdato output a a5 framer receive data (rdato). rdato is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register. rdato is the received data aligned to rfpo/rmfpo and rovrhd. rdato is updated on either the falling or rising edge of rgapclk or rsclk, depending on the value of the rsclkr bit in the ds3 master unchannelized interface options register. by default rdato will be updated on the falling edge of rgapclk or rsclk. this signal shares a signal pin with id[1] and mvid[1]. this signal will be rdato only when enabled for unchannelized ds3 operation.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 30 pin name type pin no. function rfpo/rmfpo output a b5 framer receive frame pulse/multi-frame pulse (rfpo/rmfpo). rfpo/rmfpo is valid when the temap is configured to be in framer only mode by setting the opmode[1:0] bits in the global configuration register. rfpo is aligned to rdato and indicates the position of the first bit in each ds3 m-subframe. rmfpo is aligned to rdato and indicates the position of the first bit in each ds3 m-frame. this is selected by setting the rxmfpo bit in the master framer configuration registers. rfpo/rmfpo is updated on eit her the falling or rising edge of rsclk depending on the setting of the rsclkr bit in the ds3 master unchannelized interface options register. this signal shares a signal pin with ifp[1]. when enabled for unchannelized ds3 operation this signal will be rfpo/rmfpo, otherwise it will be ifp[1]. rovrhd output y6 framer receive overhead (rovrhd). rovrhd is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register. rovrhd will be high whenever the data on rdato corresponds to an overhead bit position. rovrhd is updated on the either the fa lling or rising edge of rsclk depending on the setting of the rsclkr bit in the ds3 master unchannelized interface options register. this signal shares a signal pin with id[2]. this signal will be rovrhd only when enabled for unchannelized ds3 operation.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 31 pin name type pin no. function tfpo/tmfpo/ tgapclk output a b3 framer transmit frame pulse/multi-frame pulse reference (tfpo/tmfpo). tfpo/tmfpo is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register and setting the txgapen bit to 0 in the ds3 master unchannelized interface options register. tfpo pulses high for 1 out of every 85 clock cycles, giving a reference m-subframe indication. tmfpo pulses high for 1 out of every 4760 clock cycles, giving a reference m-frame indication. tfpo/tmfpo is updated on the falling edge of ticlk. tfpo/tmfpo can be configured to be updated on the rising edge of ticlk by setting the tdatifall bit to 1in the ds3 master unchannelized interface options register.. framer gapped transmit clock (tgapclk). tgapclk is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register and setting the txgapen bit to 1 in the ds3 master unchannelized interface options register. tgapclk is derived from the transmit reference clock ticlk or from the receive clock if loop-timed. the overhead bit (gapped) positions are generated internal to the device. tgapclk is held high during the overhead bit positions. this clock is useful for interfacing to devices which source payload data only. tgapclk is used to sample tdati and tfpi/tmfpi when txgapen is set to 1. this signal shares a signal pin with eclk[1]. when enabled for unchannelized ds3 operation this signal will be tfpo/tmfpo/tgapclk, otherwise it will be eclk[1].
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 32 pin name type pin no. function tdati input a b4 framer transmit data (tdati). tdati contains the serial data to be transmitted when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register. tdati is sampled on the rising edge of ticlk if the txgapen bit in the ds3 master unchannelized interface options register is logic 0. if txgapen is logic 1, then tdati is sampled on the rising edge of tgapclk. tdati can be configured to be sampled on the falling edge of ticlk or tgapclk by setting the tdatifall bit in the ds3 master unchannelized interface options register. this signal shares a signal pin with ed[1] and mved[1]. this signal w ill be tdati only when enabled for unchannelized ds3 operation. tfpi/tmfpi input a a3 framer transmit frame pulse/multiframe pulse (tfpi/tmfpi). tfpi/tmfpi is valid when the temap is configured as a ds3 framer by setting the opmode[1:0] bits in the global configuration register. tfpi indicates the position of all overhead bits in each ds3 m-subframe. tfpi is not required to pulse at every frame boundary. tmfpi indicates the position of the first bit in each ds3 m-frame. tmfpi is not required to pulse at every multiframe boundary. tfpi/tmfpi is sampled on the rising edge of ticlk if the txgapen bit in the ds3 master unchannelized interface options register is logic 0. if txgapen is logic 1, then tfpi/tmfpi is sampled on the rising edge of tgapclk. tfpi/tmfpi can be configured to be sampled on the falling edge of ticlk or tgapclk by setting the tdatifall bit to 1in the ds3 master unchannelized interface options register. this signal shares a signal pin with ed[2]. this signal will be tfpi/tmfpi only when enabled for unchannelized ds3 operation.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 33 pin name type pin no. function t1 and e1 system side serial clock and data interface iclk[1] iclk[2] iclk[3] iclk[4] iclk[5] iclk[6] iclk[7] iclk[8] iclk[9] iclk[10] iclk[11] iclk[12] iclk[13] iclk[14] iclk[15] iclk[16] iclk[17] iclk[18] iclk[19] iclk[20] iclk[21] iclk[22] iclk[23] iclk[24] iclk[25] iclk[26] iclk[27] iclk[28] output y3 a b2 a b20 a b21 w22 y20 h22 f19 w3 a a1 h3 h1 l22 k19 f22 g20 t3 u1 d1 c1 h19 g19 e19 f21 k3 j4 e3 d2 ingress clocks (iclk[1:28]). the ingress clocks are active when the external signaling interface is disabled. each ingress clock is optionally a smoothed (jitter attenuated) version of the associated receive clock from either the sonet/sdh mapper or the ds3 multiplexer. when the clock master: nxchannel mode is active, iclk[x] is a gapped version of the smoothed receive clock. when clock master: full t1/e1 mode is active, ifp[x] and id[x] are updated on the active edge of iclk[x]. when the clock master: nxds0 mode is active, id[x] is updated on the active edge of iclk[x]. in e1 mode only iclk[1:21] is used. iclk[1] shares a pin with the ds3 system interface signal rgapclk/rsclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 34 pin name type pin no. function id[1] id[2] id[3] id[4] id[5] id[6] id[7] id[8] id[9] id[10] id[11] id[12] id[13] id[14] id[15] id[16] id[17] id[18] id[19] id[20] id[21] id[22] id[23] id[24] id[25] id[26] id[27] id[28] output a a5 y6 a a20 t19 r19 p20 g22 g21 y2 w2 g4 h2 p21 p22 a 12 d12 u2 v4 d11 a 11 m19 l19 d10 a 10 j1 h4 b10 c10 ingress data (id[1:28]). each id[x] signal contains the recovered data stream. id[x] is aligned to the receive line timing and is updated on the active edge of the associated iclk[x]. in e1 mode only id[1:21] are used. id[1] shares a pin with the ds3 system interface signal rdato. id[2] shares a pin with the ds3 system interface signal rovrhd. id[15,16,19,20,23,24,27,28] shares pins with the sbi interface bus sddata[7:0].
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 35 pin name type pin no. function ctclk input m3 common transmit clock (ctclk). this input signal is used as a reference transmit tributary clock which can be used in egress clock master: clear channel mode. depending on the configuration of the temap, ctclk may be a line rate clock (so the transmit clock is generated directly from ctclk, or from ctclk after j itter attenuation) or a multiple of 8khz (nx8khz, where 1 n 256) so long as ctclk is jitter-free when divided down to 8khz (in which case the transmit clock is derived by the djat pll using ctclk as a reference). the temap may be configured to ignore the ctclk input and utilize one of the recovered ingress clocks instead, recvclk1 and recvclk2. receive tributary clock[x] is automatically substituted for ctclk if line loopback is enabled.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 36 pin name type pin no. function ed[1] ed[2] ed[3] ed[4] ed[5] ed[6] ed[7] ed[8] ed[9] ed[10] ed[11] ed[12] ed[13] ed[14] ed[15] ed[16] ed[17] ed[18] ed[19] ed[20] ed[21] ed[22] ed[23] ed[24] ed[25] ed[26] ed[27] ed[28] input a b4 a a3 p19 n20 n21 n22 a 7 a 2 t2 r4 a 3 b4 n19 m22 d6 c7 p2 m1 d4 b6 c20 e22 a 5 b5 l1 l2 a 4 c5 egress data (ed[1:28]). the egress data streams to be transmitted are input on these pins. when the clock master clear channel mode is active, ed[x] is sampled on the active edge of eclk[x]. when the clock slave: clear channel mode is active, ed[x] is sampled on the active edge of eclk[x]. in e1 mode only ed[1:21] are used. ed[1] shares a pin with the ds3 system interface signal tdati. ed[2] shares a pin with the ds3 system interface signal tfpi/tmfpi. ed[7,8,11,12,15,16,19,20,23,24,27,28] shares pins with the sbi interface add bus signals.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 37 pin name type pin no. function eclk[1] eclk[2] eclk[3] eclk[4] eclk[5] eclk[6] eclk[7] eclk[8] eclk[9] eclk[10] eclk[11] eclk[12] eclk[13] eclk[14] eclk[15] eclk[16] eclk[17] eclk[18] eclk[19] eclk[20] eclk[21] eclk[22] eclk[23] eclk[24] eclk[25] eclk[26] eclk[27] eclk[28] i/o a b3 y4 y19 a a21 a b22 v22 t21 t22 a b1 t1 g2 g3 u21 v19 d21 c21 u4 r1 d3 f1 t20 u22 b22 d20 l3 k4 e4 f2 egress clock (eclk[1:28]). when the clock master clear channel mode is active, eclk[x] is an output and is used to sample the associated egress data, ed[x]. eclk[x] is a version of the transmit clock[x] which is generated from the receive clock or the common transmit clock, ctclk. when in clock slave: clear channel mode eclk[x] is an input and is used to sampled ed[x]. ed[x] is sampled on the active edge of the associated eclk[x]. eclk[1] shares a pin with the ds3 system interface output signal tfpo/tmfpo/tgapclk. recovered t1 and e1 clocks recvclk1 output d22 recovered clock 1 (recvclk1). this clock output is a recovered and de-jittered clock from any one of the 28 t1 framers or 21 e1 framers. recvclk2 output c22 recovered clock 2 (recvclk2). this clock output is a recovered and de-jittered clock from any one of the 28 t1 framers or 21 e1 framers. telecom line side interface
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 38 pin name type pin no. function lrefclk input w12 line reference clock (lrefclk). this signal provides reference timing for the sonet telecom bus interface. on the incoming byte interface of the telecom bus, ldc1j1v1, l ddata[7:0], lddp, ldpl, ldtpl, ldv5, ldais and lac1 are sampled of the rising edge or lrefclk. in the outgoing byte interface, ladata[7:0], ladp, lapl, lac1j1v1 and laoe are updated on the rising edge of lrefclk. this clock is nominally a 19.44mhz +/-20ppm clock with a 50% duty cycle. this clock can be external connected to srefclk. when in transparent vt mode this clock must be connected to srefclk. lac1 input w13 line add c1 frame pulse (lac1). the add bus timing signal identifies the frame and multiframe boundaries on the add data bus ladata[7:0]. lac1 is set high to mark the first c1 byte of the first transport envelope frame of the 4 frame multiframe on the ladata[7:0] bus. lac1 need not be presented on every occurrence of the multiframe . lac1 is sampled on the rising edge of lrefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 39 pin name type pin no. function lac1j1v1 output a a11 line add bus composite timing signal (lac1j1v1). the add bus composite timing signal identifies the frame, payload and tributary multiframe boundaries on the line add data bus ladata[7:0]. lac1j1v1 pulses high with the line add payload a ctive signal lapl set low to mark the first sts-1 (stm-0/au3) identification byte or equivalently the stm identification byte c1. optionally the lac1j1v1 signal pulses high with lapl set high to mark the path trace byte j1. optionally the lac1j1v1 signal pulses high on the v1 byte to indicate tributary multiframe boundaries. in a system with multiple temaps sharing the same line add bus only one device should have lac1j1v1 connected. all devices must be configured via the lock0 bits in the master sonet/sdh configuration and ttmp telecom interface configuartion registers for the same j1 location corresponding to a pointer offset of 0 or 522. lac1j1v1 is updated on the rising edge of lrefclk. laoe output a b11 line add bus output enable (laoe). the add bus output enable signal is asserted high whenever the line add bus is being driven which is co-coincident with the line add bus outputs coming out of tri-state. this pin is intended to control an external multiplexer when multiple temaps are driving the telecom add bus during their individual tributaries. this same function is accomplished with the add bus tristate drivers but increased tolerance to tributary configuration problems is possible with an external mux. this output is controlled via the laoe bit in the ttmp tributary control registers. laoe is updated on the rising edge of lrefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 40 pin name type pin no. function ladata[0] ladata[1] ladata[2] ladata[3] ladata[4] ladata[5] ladata[6] ladata[7] output tristate a b8 w7 w8 a b9 w9 y10 a a10 a b10 line add bus data (ladata[7:0]). the add bus data contains the sonet transmit payload data in byte serial format. all transport overhead bytes are set to 00h. the phase relation of the spe (vc) to the transport frame is determined by the add bus composite timing signal lac1j1v1 and is sw selectable to be either 0 or 522. ladata[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit to be transmitted). ladata[7:0] is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. ladata[7:0] is updated on the rising edge of lrefclk. ladp output tristate w10 line add bus data parity (ladp). the add bus data parity signal carries the parity of the outgoing signals. the parity calculation encompasses the ladata[7:0] bus and optionally the lac1j1v1 and lapl signals. lac1j1v1 and lapl can be included in the parity calculation by setting the inclac1j1v1 and inclapl register bits in the master sonet/sdh egress configuration register high, respectively. odd parity is selected by setting the laop register bit in the same register high and even parity is selected by setting the laop bit low. ladp is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. ladp is updated on the rising edge of lrefclk. lapl output tristate y11 line add bus payload active (lapl). the add bus payload active signal identifies the payload bytes on ladata[7:0]. lapl is set high during path overhead and payload bytes and low during transport overhead bytes. lapl is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. lapl is updated on the rising edge of lrefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 41 pin name type pin no. function lddata[0] lddata[1] lddata[2] lddata[3] lddata[4] lddata[5] lddata[6] lddata[7] input a a13 y13 w14 a b14 w15 w16 a b15 w17 line drop bus data (lddata[7:0]). the drop bus data contains the sonet/sdh receive payload data in byte serial format. lddata[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. lddata[7:0] is sampled on the rising edge of lrefclk. lddp input a b16 line drop bus data parity (lddp). the incoming data parity signal carries the parity of the incoming signals. the parity calculation encompasses the lddata[7:0] bus and optionally the ldpl signal. ldpl can be included in the parity calculation by setting the incldpl bit in the master sonet/sdh ingress configuration register high. odd parity is selected by setting the ldop bit in the master sonet/sdh ingress configuration register high and even parity is selected by setting the ldop bit low. lddp is sampled on the rising edge of lrefclk. ldc1j1v1 input y16 line drop c1/j1 frame pulse (ldc1j1v1). the input c1/j1/v1 frame pulse identifies the transport envelope, synchronous payload envelope frame boundaries and optionallly multiframe alignment on the incoming sonet stream. ldc1j1v1 is set high while ldpl is low to mark the first c1 byte of the transport envelope frame on the lddata[7:0] bus. ldc1j1v1 is set high while ldpl is high to mark each j1 byte of the synchronous payload envelope(s) on the lddata[7:0] bus. ldc1j1v1 must be present at every occurrence of the first c1 and all j1 bytes. optionally ldc1j1v1 indicates multiframe alignment when high during the first v1 bytes of each envelope. ldc1j1v1 is sampled on the rising edge of lrefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 42 pin name type pin no. function ldpl input a a16 line drop bus payload active (ldpl). the payload active signal identifies th e bytes on lddata[7:0] that carry payload bytes. ldpl is set high during path overhead and payload bytes and low during transport overhead bytes. ldpl is set high during the h3 byte to indicate a negative pointer justification and low during the byte following h3 to indicate a positive pointer justification event. ldpl is sampled on the rising edge of lrefclk. ldv5 input a b17 line drop bus v5 byte (ldv5). the incoming tributary v5 byte signal marks the various tributary v5 bytes. ldv5 marks each tributary v5 byte on the lddata[7:0] bus when high. ldv5 is sampled on the rising edge of lrefclk. ldtpl input a b13 line drop bus tributary payload active (ldtpl). the tributary payload active signal marks the bytes carrying the tributary payload which have been identified by an external payload processor. when this signal is available, the internal pointer processor can be bypassed. ldtpl is high during each tributary payload byte on the lddata[7:0] bus. in floating mode, ldtpl contains valid data only for bytes in the vc3 or vc4 virtual containers, or the sts-1 spe. it should be ignored for bytes in the transport overhead. in locked mode, ldtpl is low for transport overhead. ldtpl is sampled on the rising edge of lrefclk. ldais input a b12 line drop bus tributary path alarm indication signal (ldais). the active high tributary path alarm indication signal identifies tributaries on the incoming data stream lddata[7:0] that are in ais state. when this signal is available, the internal pointer processor can be bypassed. ldais is invalid when ldtpl is low. ldais is sampled on the rising edge of lrefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 43 pin name type pin no. function radeastck input a a17 remote alarm port e ast clock (radeastck). the remote serial alarm port east clock provides timing for the east remote serial alarm port. it is nominally a 9.72 mhz clock, but can range from 1.344 mhz to 10 mhz. inputs radeastfp and radeast are sampled on the rising edge of radeastck. radeastfp input a b18 remote alarm port east frame pulse (radeastfp). the remote serial alarm port east frame pulse is used to locate the alarm bits of the individual tributaries in the east remote serial alarm port. radeastfp is set high to mark the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 carried in radeast. radeastfp must be set high to mark every occurrence of this bit. temap will not flywheel on radeastfp in order to accommodate a variety of radeastck frequencies. radeastfp is sampled on the rising edge of radeastck. radeast input w18 remote alarm port data east (radeast). the remote serial alarm port east carries the tributary path bip-2 error count, rdi status, and rfi status in the east remote serial alarm port. the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 on radeast is marked by a high level on radeastfp. the status carried on radeast is software selectable to be reported on the rdi, rfi and rei alarms and is selectable to be associated with any tributary on the outgoing data stream ladata[7:0]. radeast is sampled on the rising edge of radeastck. radwestck input a a18 remote alarm port west clock (radwestck). the remote serial alarm port west clock provides timing for the west remote serial alarm port. it is nominally a 9.72 mhz clock, but can range from 1.344 mhz to 10 mhz. inputs radwestfp and radwest are sampled on the rising edge of radwestck.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 44 pin name type pin no. function radwestfp input a b19 remote alarm port west frame pulse (radwestfp). the remote serial alarm port west frame pulse is used to locate the alarm bits of the individual tributaries in the west remote serial alarm port. radwestfp is set high to mark the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 carried in radwest. radwestfp must be set high to mark every occurrence of this bit. temap will not flywheel on radwestfp in order to accommodate a variety of radwestck frequencies. radwestfp is sampled on the rising edge of radwestck. radwest input w19 remote alarm port data west (radwest). the remote serial alarm port west carries the tributary path bip-2 error count, rdi status, and rfi status in the west remote serial alarm port. the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 on radwest is marked by a high level on radwestfp. the status carried on radwest is software selectable to be reported on the rdi, rfi and rei alarms and is selectable to be associated with any tributary on the outgoing data stream ladata[7:0]. radwestfp is sampled on the rising edge of radwestck. clk52m input p3 52mhz clock reference (clk52m). the 52mhz clock reference is used to generate a gapped ds3 clock when demapping a ds3 from the sonet stream and also to generate a gapped ds3 clock when receiving a ds3 from the sbi bus interface. this clock has two nominal values. the first is a nominal 51.84mhz 50% duty cycle clock. the second is a nominal 44.928mhz 50% duty cycle clock. when this clock is not used this input must be connected to ground. scaleable bandwidth interconnect interface
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 45 srefclk input b7 system reference clock (srefclk). this system reference clock is a nominal 19.44mhz +/-50ppm 50% duty cycle clock. this clock is common to both the add and drop sides of the sbi bus. when passing transparent virtual tributaries between the telecom bus and the sbi bus, srefclk must be the same as lrefclk. sc1fp i/o a 6 system c1 frame pulse (sc1fp). the system c1 frame pulse is used to synchronize devices interfacing to the sbi bus. this signal is common to both the add and drop sides of the system sbi bus. by default, sc1fp is an input. the temap can alternatively be configured to generate this frame pulse - as an output on sc1fp - for use by all other devices connected to the same sbi bus. note that all devices interconnected via an sbi interface must be synchronized to an sc1fp signal from a single common source. a s an input, sc1fp is sampled on the rising edge of srefclk. it normally i ndicates sbi mutiframe alignment, and thus should be asserted for a single srefclk cycle every 9720 srefclk cycles or some multiple thereof (i.e. every 9720*n srefclk cycles, where n is a positive integer). in synchronous sbi mode, however, sc1fp is used to indicate t1/e1 signaling multiframe alignment, and thus should be asserted for a single srefclk cycle once every 12 sbi mutiframes (48 t1/e1 frames or 116640 srefclk cycles). a s an output, sc1fp is generated on the rising edge of srefclk. it normally i ndicates sbi mutiframe alignment by pulsing high once every 9720 srefclk cycles. in synchronous sbi mode, however, sc1fp is used to indicate t1/e1 signaling multiframe alignment by pulsing once every 12 sbi mutiframes (48 t1/e1 frames or 116640 srefclk cycles).
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 46 sadata[0] sadata[1] sadata[2] sadata[3] sadata[4] sadata[5] sadata[6] sadata[7] input d6 c7 d4 b6 a 5 b5 a 4 c5 system add bus data (sadata[7:0]). the system add data bus is a time division multiplexed bus which carries the t1 and ds3 tributary data is byte serial format over the sbi bus structure. this device only monitors the add data bus during the timeslots assigned to this device. sadata[7:0] is sampled on the rising edge of srefclk. this bus shares pins with ed[15,16,19,20,23,24,27,28]. sadp input a 2 system add bus data parity (sadp). the system add bus signal carries the even or odd parity for the add bus signals sadata[7:0], sapl and sav5. the temap monitors parity across all links on the add bus. sadp is sampled on the rising edge of srefclk. this signal shares a pin with signal ed[8]. sapl input b4 system add bus payload active (sapl). the add bus payload active signal indicates valid data within the sbi bus structure. this signal must be high during all octets making up a tributary. this signal goes high during the v3 or h3 octet of a tributary to indicate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 or h3 octet of a tributary to indicate positive timing adjustments between the tributary rate and the fixed sbi bus structure. the temap only monitors the add bus payload active signal during the tributary timeslots assigned to this device. sapl is sampled on the rising edge of srefclk. this signal shares a pin with signal ed[12].
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 47 sav5 input a 3 system add bus payload indicator (sav5). the add bus payload indicator locates the position of the floating payloads for each tributary within the sbi bus structure. timing differences between the tributary timing and the synchronous sbi bus are indicated by adjustments of this payload indicator relative to the fixed sbi bus structure. a ll timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the sapl signal. the temap only monitors the add bus payload indicator signal during the tributary timeslots assigned to this device. sav5 is sampled on the rising edge of srefclk. this signal shares a pin with signal ed[11]. sajust_req output tristate d7 system add bus justification request (sajust_req). the justification request signals the link layer device to speed up, slow down or maintain the rate which it is sending data to the temap. this is only used when the temap is the timing master for the tributary transmit direction. this active high signal indicates negative timing adjustments when asserted high during the v3 or h3 octet of the tributary. in response to this the link layer device sends an extra byte in the v3 or h3 octet of the next sbi bus multi-frame. positive timing adjustments are requested by asserting j ustification request high during the octet following the v3 or h3 octet. the link layer device responds to this request by not sending an octet during the v3 or h3 octet of the next multi-frame. the temap only drives the justification request signal during the tributary timeslots assigned to this device. sajust_req is updated on the rising edge of srefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 48 sddata[0] sddata[1] sddata[2] sddata[3] sddata[4] sddata[5] sddata[6] sddata[7] output tristate a 12 d12 d11 a 11 d10 a 10 b10 c10 system drop bus data (sddata[7:0]). the system drop data bus is a time division multiplexed bus which carries the t1 and ds3 tributary data is byte serial format over the sbi bus structure. this device only drives the data bus during the timeslots assigned to this device. sddata[7:0] is updated on the rising edge of srefclk. this bus shares pins with id[15,16,19,20,23,24,27,28]. sddp output tristate d9 system drop bus data parity (sddp). the system drop bus signal carries the even or odd parity for the drop bus signals sddata[7:0], sdpl and sdv5. the temap only drives the data bus parity during the timeslots assigned to this device unless configured for bus master mode. in this case, all undriven links should be driven externally with correctly generated parity. sddp is updated on the rising edge of srefclk. sdpl output tristate d8 system drop bus payload active (sdpb). the payload active signal indicates valid data within the sbi bus structure. this signal is asserted during all octets making up a tributary. this signal goes high during the v3 or h3 octet of a tributary to accommodate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 or h3 octet of a tributary to accommodate positive timing adjustments between the tributary rate and the fixed sbi bus structure. the temap only drives the payload active signal during the tributary timeslots assigned to this device. sdpl is updated on the rising edge of srefclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 49 sdv5 output tristate a 9 system drop bus payload indicator (sdv5). the payload indicator locates the position of the floating payloads for each tributary within the sbi bus structure. timing differences between the tributary timing and the synchronous sbi bus are indicated by adjustments of this payload indicator relative to the fixed sbi bus structure. a ll timing adjustments indicated by this signal are accompanied by appropriate adjustments in the sdpl signal. the temap only drives the payload indicator signal during the tributary timeslots assigned to this device. sdv5 is updated on the rising edge of srefclk. sbiact output a 8 sbi output active (sbiact). the sbi output active indicator is high whenever the temap is driving the sbi drop bus signals. this signal is used by other temaps or other sbi devices to detect sbi configuration problems by detecting other devices driving the sbi bus during the same tributary as the device listening to this signal. this output is updated on the rising edge or srefclk. sbidet[0] sbidet[1] input c8 a 7 sbi bus activity detection (sbidet[1:0]). the sbi bus activity detect input det ects tributary collisions between devices sharing the same sbi bus. each sbi device driving the bus also drives an sbi active signal (sbiact). this pair of activity detection inputs monitors the active signals from two other sbi devices. when unused this signal should be connected to ground. a collision is detected when either of sbidet[1:0] signals are active concurrently with this device driving sbiact. when collisions o ccur the sbi drivers are disabled and an interrupt is generated to signal the collision. these signals are sampled on the rising edge of srefclk. sbidet[1] is shared with se rial interface signal ed[7]. microprocessor interface
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 50 intb output od a 16 active low open-drain interrupt (intb). this signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. note that intb will remain low until all active, unmasked interrupt sources are acknowledged at their source. csb input d16 active low chip select (csb). this signal is low during temap register accesses. csb has an integral pull up resistor. rdb input b16 active low read enable (rdb). this signal is low during temap register read accesses. the temap drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low. wrb input c15 active low write strobe (wrb). this signal is low during a temap register write access. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o c14 b14 a 14 d14 c13 b13 a 13 d13 bidirectional data bus (d[7:0]). this bus provides temap register read and write accesses. a [0] a [1] a [2] a [3] a [4] a [5] a [6] a [7] a [8] a [9] a [10] a [11] a [12] a [13] input a 17 c16 d18 d19 b17 a 18 a 19 a 20 c18 b19 b20 a 21 c19 b21 address bus (a[13:0]). this bus selects specific registers during temap register accesses. signal a[13] selects between normal mode and test mode register access. a[13] has an integral pull down resistor. rstb input a 22 active low reset (rstb). this signal provides an asynchronous temap reset. rstb is a schmitt triggered input with an integral pull up resistor.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 51 a le input d17 address latch enable (ale). this signal is active high and latches the address bus a[13:0] when low. when ale is high, the internal address latches are transparent. it allows the temap to interface to a multiplexed address/data bus. the ale input has an integral pull up resistor. jtag interface tck input c3 test clock (tck). this signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input c2 test mode select (tms). this signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input c4 test data input (tdi). this signal carries test data into the temap via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor. tdo output b3 test data output (tdo). this signal carries test data out of the temap via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb input b1 active low test reset (trstb). this signal provides an asynchronous temap test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull up resistor. trstb must be asserted during the power up sequence. note that if not used, trstb must be connected to the rstb input. miscellaneous pins
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 52 no connect a 1 b2 a a2 v3 w20 a a2 2 y21 w21 k22 k21 y1 w1 f4 g1 v20 y22 k20 j19 w4 v1 e1 u19 r22 j22 j20 k1 k2 t4 a 1 b2 no connect. these pins are not connected to any internal logic.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 53 power and ground pins vdd3.3[17] vdd3.3[16] vdd3.3[15] vdd3.3[14] vdd3.3[13] vdd3.3[12] vdd3.3[11] vdd3.3[10] vdd3.3[9] vdd3.3[8] vdd3.3[7] vdd3.3[6] vdd3.3[5] vdd3.3[4] vdd3.3[3] vdd3.3[2] vdd3.3[1] power n2 a a12 l21 c12 f3 m4 u3 y5 a a9 a a14 y18 u20 m21 f20 c17 b11 d5 power (vdd3.3[17:1]). the vdd3.3[17:1] pins should be connected to a well decoupled +3.3v dc power supply. vdd2.5[8] vdd2.5[7] vdd2.5[6] vdd2.5[5] vdd2.5[4] vdd2.5[3] vdd2.5[2] vdd2.5[1] power j2 r2 a a8 a a15 r21 h21 a 15 c9 power (vdd2.5[8:1]). the vdd2.5[8:1] pins should be connected to a well-decoupled +2.5v dc power supply.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 54 vss3.3[22] vss3.3[21] vss3.3[20] vss3.3[19] vss3.3[18] vss3.3[17] vss3.3[16] vss3.3[15] vss3.3[14] vss3.3[13] vss3.3[12] vss3.3[11] vss3.3[10] vss3.3[9] vss3.3[8] vss3.3[7] vss3.3[6] vss3.3[5] vss3.3[4] vss3.3[3] vss3.3[2] vss3.3[1] ground n3 y12 l20 b12 e2 l4 v2 a a4 y9 w11 y14 y17 a a19 v21 m20 j21 e21 b18 d15 c11 b8 c6 ground (vss3.3[22:1]). the vss3.3[22:1] pins should be connected to gnd. vssq[4] vssq[3] vssq[2] vssq[1] ground n3 y12 l20 b12 ground (vssq[4:1]). the vssq[4:1] pins should be connected to gnd. vss2.5[13] vss2.5[12] vss2.5[11] vss2.5[10] vss2.5[9] vss2.5[8] vss2.5[7] vss2.5[6] vss2.5[5] vss2.5[4] vss2.5[3] vss2.5[2] vss2.5[1] n4 m2 n1 p4 p1 j3 r3 y8 y15 r20 h20 b15 b9 ground (vss2.5[13:1]). the vss2.5[13:1] pins should be connected to gnd.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 55 vss[36] vss[35] vss[34] vss[33] vss[32] vss[31] vss[30] vss[29] vss[28] vss[27] vss[26] vss[25] vss[24] vss[23] vss[22] vss[21] vss[20] vss[19] vss[18] vss[17] vss[16] vss[15] vss[14] vss[13] vss[12] vss[11] vss[10] vss[9] vss[8] vss[7] vss[6] vss[5] vss[4] vss[3] vss[2] vss[1] j14 j13 j12 j11 j10 j9 k14 k13 k12 k11 k10 k9 l14 l13 l12 l11 l10 l9 m14 m13 m12 m11 m10 m9 n14 n13 n12 n11 n10 n9 p14 p13 p12 p11 p10 p9 thermal ground (vss). the vss[36:1] pins should be connected to a ground plane for enhanced thermal conductivity. notes on pin descriptions: 1. all temap inputs and bi-directionals present minimum capacitive loading and operate at ttl logic levels. 2. all temap outputs and bi-directionals hav e at least 2 ma drive capability. the bidirectional data bus outputs, d[7:0], have 4 ma drive capability. the outputs tclk, tpos/tdat, tneg/tmfp, rgapclk/rsclk, rdatao,
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 56 rfpo/rmfpo, rovrhd, tfpo/tmfpo/tgapclk, sbiact, laoe, recvclk1, recvclk2, and intb have 4 ma drive capability. the sbi outputs and telecom bus outputs, sddata[7:0], sddp, sdpl, sdv5, sajust_req, lac1j1v1, ladata[7:0], ladp and lapl, have 8ma drive capability. the bidirectional sbi sig nal sc1fp has 8ma drive capability. 3. iol = -2ma for others. 4. inputs rstb, ale, tms, tdi, trstb and csb have internal pull-up resistors. 5. input a[13] has an internal pull-down resistor. 6. all unused inputs should be connected to ground. 7. all temap outputs can be tristated under control of the ieee p1149.1 test access port, even those which do not tristate under normal operation. all outputs and bi-directionals are 5 v tolerant when tristated. 8. power to the vdd3.3 and vddq pins should be applied before power to the vdd2.5 pins is applied. similarly, power to the vdd2.5 pins should be removed before power to the vdd3.3 and vddq pins are removed. 9. all temap inputs are 5v tolerant.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 57 9 functional description 9.1 t1 framer (t1-frmr) the t1 framing function is provided by the t1-frmr block. this block searches for the framing bit position in the ingress stream. it works in conjunction with the fram block to search for the framing bit pattern in the standard superframe (sf), or extended superframe (esf) framing formats. when searching for frame, the frmr simultaneously examines each of the 193 (sf) or each of the 772 (esf) framing bit candidates. the fram block is addressed and controlled by the frmr while frame synchronization is acquired. the time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0) , is dependent upon the framing format. for sf format, the t1-frmr block will determine frame alignment within 4.4ms 99 times out of 100. for esf format, the t1-frmr will determine frame alignment within 15 ms 99 times out of 100. once the t1-frmr has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in sf or a crc-6 error in esf), and severely errored framing events. the t1-frmr also detects out-of- frame, based on a selectable ratio of framing bit errors. the t1-frmr can also be disabled to allow reception of unframed data. 9.2 e1 framer (e1-frmr) the e1 framing function is provided by the e1-frmr block. the e1-frmr block searches for basic frame alignment, crc multiframe alignment, and channel associated signaling (cas) multiframe alignment in the incoming recovered pcm stream. once the e1-frmr has found basic (or fas) frame alignment, the incoming pcm data stream is continuously monitored for fas/nfas framing bit errors. framing bit errors are accumulated in the framing bit error counter contained in the pmon block. once the e1-frmr has found crc multiframe alignment, the pcm data stream is continuously monitored for crc multiframe alignment pattern errors, and crc-4 errors. crc-4 errors are accumulated in the crc error counter of the pmon block. once the e1-frmr has found cas multiframe alignment, the pcm data is continuously monitored for cas multiframe alignment pattern errors. the e1-frmr also detects and indicates loss of basic frame, loss of crc multiframe, and loss of cas multiframe, based
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 58 on user-selectable criteria. the reframe operation can be initiated by software (via the e1-frmr frame alignment options register), by excessive crc errors, or when crc multiframe alignment is not found within 400 ms. the e1-frmr also identifies the position of the frame, the cas multiframe, and the crc multiframe. the e1-frmr extracts the contents of the international bits (from both the fas frames and the nfas frames), the national bits, and the extra bits (from timeslot 16 of frame 0 of the cas multiframe), and stores them in the e1-frmr international/national bits register and the e1-frmr extra bits register. moreover, the frmr also extracts submultiframe-aligned 4-bit codewords from each of the national bit positions sa4 to sa8, and stores them in microprocessor-accessible registers that are updated every crc submultiframe. the e1-frmr identifies the raw bit values for the remote (or distant frame) alarm (bit 3 in timeslot 0 of nfas frames) and the remote signaling multiframe (or distant multiframe) alarm (bit 6 of timeslot 16 of frame 0 of the cas multiframe) via the e1-frmr international/national bits register, and the e1-frmr extra bits register respectively. access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per recommendation o.162. detection of ais and timeslot 16 ais are provided. ais is also integrated, and an ais alarm is indicated if the ais condition has persisted for at least 100 ms. the out of frame (oof=1) condition is also integrated, indicating a red alarm if the oof condition has persisted for at least 100 ms. an interrupt may be generated to signal a change in the state of any status bits (oof, oosmf, oocmf, ais or red), and to signal when any event (rai, rmai, aisd, ts16aisd, cofa, fer, smfer, cm fer, crce or febe) has occurred. additionally, interrupts may be generated every frame, crc submultiframe, crc multiframe or signaling multiframe. basic frame alignment procedure the e1-frmr searches for basic frame a lignment using the algorithm defined in itu-t recommendation g.706 sections 4.1.2 and 4.2.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 59 the algorithm finds frame alignment by using the following sequence: 1. search for the presence of the correct 7-bit fas (?0011011?); 2. check that the fas is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (nfas) ts 0 byte is a logic 1; 3. check that the correct 7-bit fas is present in the assumed ts 0 byte of the next frame. if either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit fas sequence check. this "hold-off" is done to ensure that new frame alignment searches are done in the nex t bit position, modulo 512. this facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the fas. once frame alignment is found, the block sets the oof indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit fas pattern and in bit 2 of nfas frames, and indicating the debounced value of the remote alarm bit (bit 3 of nfas frames). using debounce, the remote alarm bit has <0.00001% probability of being falsely indi cated in the presence of a 10 -3 bit error rate. the block declares loss of frame alignment if 3 consecutive fass have been received in error or, additionally, if bit 2 of nfas frames has been in error for 3 consecutive occasions. in the presence of a random 10 -3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. the e1-frmr can be forced to initiate a basic frame search at any time when any of the following conditions are met: the software re-frame bit in the e1-frmr frame alignment options register goes to logic 1; the crc frame find block is unable to find crc multiframe alignment; or the crc frame find block accumulates excessive crc evaluation errors ( 915 crc errors in 1 second) and is enabled to force a re-frame under that condition. crc multiframe alignment procedure the e1-frmr searches for crc multiframe alignment by observing whether the international bits (bit 1 of ts 0) of nfas frames follow the crc multiframe alignment pattern. multiframe alignment is declared if at least two valid crc
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 60 multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms once crc multiframe alignment is found, the oocmfv register bit is set to logic 0, and the e1-frmr monitors the multiframe alignment signal, indicating errors occurring in the 6-bit mfas pattern, errors occurring in the received crc and the value of the febe bits (bit 1 of frames 13 and 15 of the multiframe). the e1-frmr declares loss of crc multiframe alignment if basic frame alignment is lost. however, once crc multiframe alignment is found, it cannot be lost due to errors in the 6-bit mfas pattern. under the crc-to-non-crc interw orking algorithm, if the e1-frmr can achieve basic frame alignment with respect to the incoming pcm data stream, but is unable to achieve crc-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non crc-4 interface. the details of this algorithm are illustrated in the state diagram in figure 7.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 61 figure 7 - crc multiframe alignment algorithm fas_find_1 nfas_find fas_find_2 bf a crcto crc interworking fas_f ind_1_par nfas_find_par fas_find_2_par bf a _ par crcto non-crc interworking fa s found nf as found nex t fram e fa s found nex t fram e cr cmf a nf as not found nex t fram e fa s not found next fram e fa s found nf as not found nex t fram e fa s not found nex t fram e nf as found nex t fram e 400m s expire fa s found nex t fram e start 400ms timer and 8ms timer 8ms ex pire 8ms expire and not( 400 ms exp ire) cr cm fa_ par start 8ms timer reset bf a to most recently found alignment out of frame cr cm fa_ par ( o p tional settin g) 3 consecutive fasor nf a s errors; manual reframe; or excessive crc errors
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 62 table 1 - e1-frmr framing states state out of frame out of offline frame fas_find_1 yes no nfas_find yes no fas_find_2 yes no bfa no no crc to crc interworking no no fas_find_1_par no yes nfas_find_par no yes fas_find_2_par no yes bfa_par no no crc to non-crc interworking no no the states of the primary basic framer and the parallel/offline framer in the e1-frmr block at each stage of the crc multiframe alignment algorithm are shown in table 1. from an out of frame state, the e1-frmr attempts to find basic frame alignment in accordance with the fas/nfas/fas g.706 basic frame alignment procedure outlined above. upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. if two crc multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, crc multiframe alignment is declared. if the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. this search is performed in accordance with the basic frame alignment procedure outlined above. however, this search does not immediately change the actual basic frame alignment of the system (i.e., pcm data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). when a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. if two crc multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, crc multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found crc multiframe alignment). subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. if, however, the 400 ms timer expires at any time during this procedure, the e1-frm r stops searching for crc multiframe alignment and declares crc-to-non-crc interworking. in this mode, the e1-frmr may be optionally set to either halt searching for crc multiframe altogether, or may
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 63 continue searching for crc multiframe a lignment using the established basic frame alignment. in either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once crc-to-non-crc interworking is declared: it is assumed that the established basic frame alignment at this point is correct. ais detection when an unframed all-ones receive data stream is received, an ais defect is indicated by setting the aisd bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optiona lly, in each of two consecutive periods of 512 bits. the aisd bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consec utive periods of 512 bits. finding frame alignment will also cause the aisd bit to be set to logic 0. signaling frame alignment once the basic frame alignment has been found, the e1-frmr searches for channel associated signaling (cas) multiframe alignment using the following g.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct cas alignment pattern, namely four zeros (?0000?) in the first four bit positions of timeslot 16. once signaling multiframe alignment has been found, the e1-frmr sets the oosmfv bit of the e1-frmr framing status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the remote signaling multiframe alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). using debounce, the remote signaling multif rame alarm bit has < 0. 00001% probability of being falsely indicated in the presence of a 10 -3 bit error rate. the block declares loss of cas multiframe alignment if two consecutive cas multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) cas multiframes. loss of cas multiframe alignment is also declared if basic frame alignment has been lost. national bit extraction the e1-frmr extracts and assembles the submultiframe-aligned national bit codewords sa4[1:4] , sa5[1:4] , sa6[1:4] , sa7[1:4] and sa8[1:4]. the corresponding register values are updated upon generation of the crc submultiframe interrupt.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 64 this e1-frmr also detects the v5.2 link id signal, which is detected when 2 out of 3 sa7 bits are zeros. upon reception of this link id signal, the v52linkv bit of the e1-frmr framing status register is set to logic 1. this bit is cleared to logic 0 when 2 out of 3 sa7 bits are ones. alarm integration the oof and the ais defects are integrat ed, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. the alarm is removed when the condition has been absent for 104 ms ( 6 ms). the ais alarm algorithm accumulates the occurrences of aisd (ais detection). the e1-frmr counts the occurrences of aisd over a 4 ms interval and indicates a valid ais is present when 13 or more aisd indications (of a possible 16) have been received. each interval with a valid ais presence indication increments an interval counter which declares ais alarm when 25 valid intervals have been accumulated. an interval with no valid ais presence indication decrements the interval counter. the ais alarm declaration is removed when the counter reaches 0. this algorithm provides a 99.8% probability of declaring an ais alarm within 104 ms in the presence of a 10 -3 mean bit error rate. the red alarm algorithm monitors occurrences of oof over a 4 ms interval, indicating a valid oof interval when one or more oof indications occurred during the interval, and indicating a valid in frame (inf) interval when no oof indication occurred for the entire interval. each interval with a valid oof indication increments an interval counter which declares red alarm when 25 valid intervals have been accumulated. an interval with valid inf indication decrements the interval counter; the red alarm declaration is removed when the counter reaches 0. this algorithm biases oof occurrences, leading to declaration of red alarm when intermittent loss of frame alignment occurs. the e1-frmr can also be disabled to allow reception of unframed data. 9.3 performance monito r counters (t1/e1-pmon) the performance monitor counters function is provided by the pmon block. the block accumulates crc error events, frame synchronization bit error events, and out of frame events, or optionally, change of frame alignment (cofa) events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). when the transfer clock signal is applied, the pmon transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. the counters are reset in such a manner that error events occurring during the reset are not missed. if the holding registers are not read between successive transfer clocks, an ove rrun register bit is asserted.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 65 generation of the transfer clock within the temap chip is performed by writing to any counter register location or by writing to the global pmon update register. the holding register addr esses are contiguous to facilitate faster polling operations. 9.4 t1 alarm integrator (almi) the t1 alarm integration function is provided by the almi block. this block detects the presence of yellow, red, and ais carrier fail alarms (cfa) in sf, or esf formats. the alarm detection and integration is compatible with the specifications defined in ansi t1.403 and tr-tsy-000191. the almi block declares the presence of yellow alarm when the yellow pattern has been received for 425 ms ( 50 ms); the yellow alarm is removed when the yellow pattern has been absent for 425 ms ( 50 ms). the presence of red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). the presence of ais alarm is declared when an out-of-frame condition and all-ones in the pcm data stream have been present for 1.5 sec (100 ms); the ais alarm is removed when the ais condition has been absent for 16.8 sec (500 ms). cfa alarm detection algorithms operate in the presence of a 10 -3 bit error rate. the almi also indicates the presence or absence of the yellow, red, and ais alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. alarm indication is provided through internal register bits. 9.5 receive and transmit digital jitter attenuator (rjat, tjat) the digital jitter attenuation function is provided by the djat blocks. each framer in the temap contains two separate jitter attenuators, one between the receive demultiplexed or demapped t1 or e1 link and the ingress interface (rjat) and the other between the egress interface and the transmit t1 or e1 link to be multiplexed into ds3 or mapped into sonet (tjat). each djat block receives jittered data and stores the stream in a fifo timed to the associated receive jittered clock. the jitter attenuated data emerges from the fifo timed to the jitter attenuated clock. in the rjat, the jitter attenuated clock (iclk[x]) is referenced to the demultiplexed or demapped tributary receive clock. in the tjat, the jitter attenuated transmit tributary clock feeding the m13 multiplexer or sonet/sdh mapper may be referenced to either ctclk or the tributary receive clock.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 66 in t1 mode each jitter attenuator generates its output clock by adaptively dividing the 37.056 mhz xclk signal according to the phase difference between the jitter attenuated clock and the input reference clock. jitter fluctuations in the phase of the reference clock are attenuated by the phase-locked loop within each djat so that the frequency of the jitter attenuated clock is equal to the average frequency of the reference. to best fit the jitter attenuation transfer function recommended by tr 62411, phase fluctuations with a jitter frequency above 6.6 hz are attenuated by 6 db per octave of jitter frequency. wandering phase fluctuations with frequencies below 6.6 hz are tracked by the jitter attenuated clock. the jitter attenuated clock (iclk[x] for the rjat and transmit clock for the tjat) are used to read data out of the fifo. in e1 mode each jitter attenuator generates the jitter-free 2.048 mhz output clock by adaptively dividing the 49.152 mhz xclk signal according to the phase difference between the jitter attenuated clock and input reference clock. fluctuations in the phase of the input data clock are attenuated by the phase- locked loop within djat so that the frequency of the jitter attenuated clock is equal to the average frequency of the input data clock. phase fluctuations with a jitter frequency above 8.8 hz are attenuated by 6 db per octave of jitter frequency. wandering phase fluctuations with frequencies below 8.8 hz are tracked by the jitter attenuated clock. to provide a smooth flow of data out of djat, the jitter attenuated clock is used to read data out of the fifo. the tjat and rjat have programmable divisors in order to generate the jitter attenuated clock from the various reference sources. the divisors are set using the tjat and rjat jitter attenuator divider n1 and n2 registers. the following formula must be met in order to select the values of n1 and n2: fin/(n1 + 1) = fout/(n2 + 1) where fin is the input reference clock frequency and fout is the output jitter attenuated clock frequency. the values on n1 and n2 can range between 1 and 256. fin ranges from 8khz to 2.048mhz in 8khz increments. if the fifo read pointer comes within one bit of the write pointer, djat will track the jitter of the input clock. this permits the phase jitter to pass through unattenuated, inhibiting the loss of data. jitter characteristics each djat block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. in t1 mode each djat can accommodate up to 28 uipp of input jitter at jitter frequencies above 6 hz. for jitter frequencies below 6 hz, more correctly called wander, the tolerance increases 20 db per decade. in e1 mode each djat can accommodate up to 35 uipp of input jitter at
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 67 jitter frequencies above 9 hz. for jitter frequencies below 9 hz, more correctly called wander, the tolerance increases 20 db per decade. in most applications the each djat block will limit jitter toler ance at lower jitter frequencies only. for high frequency jitter, above 10 khz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. for low frequency wander, below 10 hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. the djat blocks meet the stringent low frequency ji tter tolerance requirements of at&t tr 62411, itu-t recommendation g.823 and thus allow compliance with this standard and the other less stringent jitter tolerance standards cited in the references. the djat exhibits negligible jitter gain for jitter frequencies below 6.6 hz, and attenuates jitter at frequencies above 6.6 hz by 20 db per decade in t1 mode. it exhibits negligible jitter gain for jitter frequencies below 8.8 hz, and attenuates jitter at frequencies above 8.8 hz by 20 db per decade in e1 mode. in most applications the djat blocks will determi ne jitter attenuation for higher jitter frequencies only. wander, below 10 hz for example, will essentially be passed unattenuated through djat. jitter, above 10 hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. this generated residual jitter is directly related to the use of 24x (37.056 mhz or 49.152 mhz) digital phase locked loop for transmit clock generation. djat meets the jitter transfer requirements of at&t tr 62411. the djat allows the implied t1 jitter attenuation requirements for a te or nt1 given in ansi standard t1.408, and the implied jitter attenuation requirements for a type ii customer interface given in ansi t1.403 to be met. the djat meets the e1 jitter attenuation requirements of the itu-t recommendations g.737, g.738, g.739 and g.742. jitter tolerance jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. for t1 modes the djat input jitter tolerance is 29 unit intervals peak-to- peak (uipp) with a worst case frequency offset of 354 hz. for e1 modes the input jitter tolerance is 35 unit intervals peak-to-peak (uipp) with a worst case frequency offset of 308 hz. in either mode jitter tolerance is 48 uipp with no frequency offset. the frequency offset is the difference between the frequency of xclk divided by 24 and that of the input data clock.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 68 figure 8 - djat jitter tolerance t1 modes 100 10 1.0 0.1 110 100 1k 10k jitter frequency, hz jitter a mplitude, uipp 0.01 100k 28 29 acceptable unacceptable 0.2 4.9 0.3k djat minimum tolerance
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 69 figure 9 - djat jitter tolerance e1 modes the accuracy of the xclk frequency and that of the reference clock used to generate the jitter attenuated clock have an effect on the minimum jitter tolerance. given that the djat pll reference clock accuracy can be 200 hz from 1.544 mhz or be 103 hz from 2.048 mhz, and that the xclk input accuracy can be 100 ppm from 37.056 mhz or 100 ppm from 49.152 mhz, the minimum jitter tolerance for various differences between the frequency of pll reference clock and xclk 24 are shown in figure 10 and figure 11. an xclk input accuracy of 100 ppm is only acceptable if an accurate line rate reference is provided. if tjat is left to free-run without a reference, or referenced to a derivative of xclk, then xclk accuracy must be 32 ppm.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 70 figure 10 - djat minimum jitter tolerance vs. xclk accuracy t1 modes figure 11 - djat minimum jitter tolerance vs. xclk accuracy e1 modes
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 71 jitter transfer the output jitter in t1 mode for jitter frequencies from 0 to 6.6 hz is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 6.6 hz are attenuated at a level of 6 db per octave, as shown in figure 12. figure 12 - djat jitter transfer t1 modes the output jitter in e1 mode for jitter frequencies from 0 to 8.8 hz is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 8.8 hz are attenuated at a level of 6 db per octave, as shown in figure 13.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 72 figure 13 - djat jitter transfer e1 modes frequency range in the non-attenuating mode for t1 rates, that is, when the fifo is within one ui of overrunning or under running, the tracking range is 1.48 to 1.608 mhz. the guaranteed linear operating range for the jittered input clock is 1.544 mhz 200 hz with worst case jitter (29 uipp) and maximum xclk frequency offset ( 100 ppm). the nominal range is 1.544 mhz 963 hz with no jitter or xclk frequency offset. in the non-attenuating mode for e1 rates the tracking range is 1.963 to 2.133 mhz. the guaranteed linear operating range for the jittered input clock is 2.048 mhz 1278 hz with worst case jitter (42 uipp) and maximum xclk frequency offset ( 100 ppm). 9.6 timing options (tops) the timing options block provides a means of selecting the source of the internal input clock to the tjat block, the reference clock for the tjat digital pll, and the clock source used to derive the transmit clock to the m13 mux or sonet/sdh mapper.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 73 9.7 pseudo random binary sequence generation and de tection (prbs) the pseudo random binary sequence generator/detector (prbs) block is a software selectable prbs generator and checker for 2 11 -1, 2 15 -1 or 2 20 -1 prbs polynomials for use in the t1 and e1 links. prbs patterns may be generated in either the transmit or receive directions, and detected in the opposite direction. the prbs block can perform an auto synchronization to the expected prbs pattern and accumulates the total number of bit errors in two 24-bit counters. the error count accumulates over the interval defined by to the global pmon update register. when an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. the counter is reset in such a way that no events are missed. the data is then available in the error count registers until the next accumulation. 9.8 pseudo random pattern gene ration and det ection (prgd) the pseudo random pattern generator/detector (prgd) block is a software programmable test pattern generator, receiver, and analyzer for the ds3 payload. patterns may be generated in the transmit direction, and detected in the receive direction. two types of itu-t o.151 compliant test patterns are provided : pseudo-random and repetitive. the prgd can be programmed to generate any pseudo-random pattern with length up to 2 32 -1 bits or any user programmable bit pattern from 1 to 32 bits in length. in addition, the prgd can insert single bit errors or a bit error rate between 10 -1 to 10 -7 . the prgd can be programmed to check for the generated pseudo random pattern. the prgd can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. the counters accumulate either over intervals defined by writes to the pattern detector registers, upon writes to the global pmon update register or automatically once a second. when an accumulation is forced, the holding registers are updated, and the counters reset to begin accumulating for the next interval. the counters are reset in such a way that no events are missed. the data is then available in the holding registers until the next accumulation. 9.9 ds3 framer (ds3-frmr) the ds3 framer (ds3-frmr) block integrates circuitry required for decoding a b3zs-encoded signal and framing to the resulting ds3 bit stream. the ds3-frmr is directly compatible with the m23 and c-bit parity ds3 applications.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 74 the ds3-frmr decodes a b3zs-encoded signal and provides indications of line code violations. the b3zs decoding algorithm and the lcv definition can be independently chosen through software. a loss of signal (los) defect is also detected for b3zs encoded streams. los is declared when inputs rpos and rneg contain zeros for 175 consecutive rclk cycles. los is removed when the ones density on rpos and/or rneg is greater than 33% for 175 1 rclk cycles. the framing algorithm examines five f-bit candidates simultaneously. when at least one discrepancy has occurred in eac h candidate, the algorithm examines the next set of five candidates. when a single f-bit candidate remains in a set, the first bit in the supposed m-subframe is examined for the m-frame alignment signal (i.e., the m-bits, m1, m2, and m3 are following the 010 pattern). framing is declared, and out-of-frame is removed, if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f-bits. during the examination of the m-bits, the x-bits and p-bits are ignored. the algorithm gives a maximum average reframe time of 1.5 ms. while the ds3-frmr is synchronized to the ds3 m-frame, the f-bit and m-bit positions in the ds3 stream are examined. an out-of-frame defect is detected when 3 f-bit errors out of 8 or 16 consecutive f-bits are observed (as selected by the m3o8 bit in the ds3 frmr configuration register), or when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames. the m-bit error criteria for oof can be disabled by the mbdis bit in the ds3 framer configuration register. the 3 out of 8 consecutive f-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive f-bits ratio. either out-of-frame criteria allows an out-of- frame defect to be detected quickly when the m-subframe alignment patterns or, optionally, when the m-frame alignment pattern is lost. also while in-frame, line code violations, m-bit or f-bit framing bit errors, and p- bit parity errors are indicated. when c-bit parity mode is enabled, both c-bit parity errors and far end block errors are indicated. these error indications, as well as the line code violation and excessive zeros indication, are accumulated over 1 second intervals with the performance monitor (pmon). note that the framer is an off-line framer, indicating both oof and cofa events. even if an oof is indicated, the framer will cont inue indicating performance monitoring information based on the previous frame alignment. three ds3 maintenance signals (a red alarm condition, the alarm indication signal, and the idle signal) are detected by the ds3-frmr. the maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" m-frame intervals. for the red alarm, an m-frame is said to be a "valid" interval if it contains a red defect, defined as an occurrence of an oof or los event during that m-frame. for ais and idle, an m-frame
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 75 interval is "valid" if it contains ais or idle, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for ais, 1100... for idle) while valid frame alignment is maintained. this discrepancy threshold ensures the detection algorithms operate in the presence of a 10 -3 bit error rate. for ais, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary ds3 signal and the c-bits all zero; the framed "1010" signal and the c-bits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). each "valid" m- frame causes an associated integration counter to increment; "invalid" m-frames cause a decrement. with the "slow" detection option, red, ais, or idle are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. with the "fast" detection option, red, ais, or idle are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). red, ais, or idle are removed when the respective counter decrements to 0. ds3 loss of frame detection is provided as recommended by itu-t g.783 with programmable integration periods of 1ms, 2ms, or 3ms. while integrating up to assert lof, the counter will integrate up when the framer asserts an out of frame condition and integrates down when the framer de-asserts the out of frame condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is deasserted. valid x-bits are extracted by the ds3-frmr to provide indication of far end receive failure (ferf). a ferf defect is detected if the extracted x-bits are equal and are logic 0 (x1=x2=0); the defect is removed if the extracted x-bits are equal and are logic 1 (x1=x2=1). if the x-bits are not equal, the ferf status remains in its previous state. the extracted ferf status is buffered for 2 m- frames before being reported within the ds3 frmr status register. this buffer ensures a better than 99.99% chance of freezing the ferf status on a correct value during the occurrence of an out of frame. when the c-bit parity application is enabled, both the far end alarm and control (feac) channel and the path maintenance data link are extracted. codes in the feac channel are detected by the bit oriented code detector (rboc). hdlc messages in the path maintenance data link are received by the data link receiver (rdlc). the ds3-frmr can be enabled to automatically assert the rai indication in the outgoing transmit stream upon detection of any combination of los, oof or red, or ais. the ds3-frmr can also be enabled to automatically insert c-bit parity febe upon detection of receive c-bit parity error. the ds3-frmr may be configured to generate interrupts on error events or status changes. all sources of interrupts can be masked or acknowledged via
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 76 internal registers. internal registers are also used to configure the ds3-frmr. access to these registers is via a generic microprocessor bus. 9.10 performance monitor accumulator (ds3-pmon) the performance monitor (pmon) block interfaces directly with the ds3 framer (ds3-frmr). saturating counters are used to accumulate: line code violation (lcv) events parity error (perr) events path parity error (cperr) events far end block error (febe) events excess zeros (exzs) framing bit error (ferr) events due to the off-line nature of the ds3 framer, pmon continues to accumulate performance meters even while the ds3-frmr has declared oof. when an accumulation interval is signaled by a write to the pmon register address space, the pmon transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. the counters are reset in such a manner that error events occurring during the reset period are not missed. when counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. if the holding registers have not been read since the last interrupt, an overrun status bit is set. in addition, a register is provided to indicate changes in the pmon counters since the last accumulation interval. whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. if the holding registers have not been read since the last interrupt, an overrun status bit is set. 9.11 ds3 transmitter (ds3-tran) the ds3 transmitter (ds3-tran) block integrates circuitry required to insert the overhead bits into a ds3 bit stream and produce a b3zs-encoded signal. the t3-tran is directly compatible with the m23 and c-bit parity ds3 formats.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 77 when configured for the c-bit parity application, all overhead bits are inserted. when configured for the m23 application, all overhead bits except the stuff control bits (the c-bits) are inserted; the c-bits are inserted by the upstream mx23 tsb. status signals such as far end receive failure (ferf), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. ferf can also be automatically inserted on detection of any combination of los, oof or red, or ais by the ds3-frmr. a valid pair of p-bits is automatically calculated and inserted by the ds3-tran. when c-bit parity mode is selected, the path parity bits, and far end block error (febe) indications are automatically inserted. when enabled for c-bit parity operation, the feac channel is sourced by the xboc bit-oriented code transmitter. the path maintenance data link messages are sourced by the tdpr data link transmitter. the ds3-tran supports diagnostic modes in which it inserts parity or path parity errors, f-bit framing errors, m-bit framing errors, invalid x or p-bits, line code violations, or all-zeros. 9.12 m23 multiplexer (mx23) the m23 multiplexer (mx23) integrates circuitry required to asynchronously multiplex and demultiplex seven ds2 streams into, and out of, an m23 or c-bit parity formatted ds3 serial stream. when multiplexing seven ds2 streams into an m23 formatted ds3 stream, the mx23 tsb performs rate adaptation to the ds3 by integral fifo buffers, controlled by timing circuitry. the c-bits are also generated and inserted by the timing circuitry. software control is provided to transmit ds2 ais and ds2 payload loopback requests. the loopback request is coded by inverting one of the three c-bits (the default option is compatible with ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7). the tsb also supports generation of a c-bit parity formatted ds3 stream by providing an internally generated ds2 rate clock corresponding to a 100% stuffing ratio. integrated m13 applications are supported by providing an internally generated ds2 rate clock corresponding to a 39.1% stuffing ratio. when demultiplexing seven ds2 streams from an m23 formatted ds3, the mx23 performs bit destuffing via interpretation of the c-bits. the mx23 also detects and indicates ds2 payload loopback requests encoded in the c-bits. as per ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7, the loopback command is identified as c3 being the inverse of c1 and c2. because tr-tsy-
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 78 000233 section 5.3.14.1 recommends compat ibility with non-compliant existing equipment, the two other loopback command po ssibilities are also supported. as per tr-tsy-000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has been absent for five successive m-frames. ds2 payload loopback can be activated or deactivated under software control. during payload loopback the ds2 str eam being looped back still continues unaffected in the demultiplex direction to the ds2 framer. all seven demultiplexed ds2 streams can also be replaced with ais on an individual basis under register control or they can be configured to be replaced automatically on detection of out of frame, loss of signal, red alarm or alarm indication signal. 9.13 ds2 framer (ds2-frmr) the frmr ds2 framer integrates circuitry required for framing to a ds2 bit stream and is directly compatible with the m12 ds2 application. the frmr can also be configured to frame to a g.747 bit stream. the ds2 frmr frames to a ds2 signal with a maximum average reframe time of less than 7 ms and frames to a g.747 signal with a maximum average reframe time of 1 ms. in ds2 mode, both the f-bits and m-bits must be correct for a significant period of time before frame alignment is declared. in g.747 mode, frame alignment is declared if the candidate frame alignment signal has been correct for 3 consecutive frames (in accordance with ccitt rec. g.747 section 4). once in frame, the ds2 frmr provides indications of the m-frame and m- subframe boundaries, and identifies the overhead bit positions in the incoming ds2 signal or provides indications of the frame boundaries and overhead bit positions in the incoming g.747 signal. depending on configuration, declaration of ds2 out-of-frame occurs when 2 out of 4 or 2 out of 5 consecutive f-bits are in error (these two ratios are recommended in tr-tsy-000009 section 4.1.2) or when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames. the m-bit error criteria for oof can be disabled via the mbdis bit in the ds2 framer configuration register. in g.747 mode, out-of-frame is declared when four consecutive frame alignment signals are incorrectly received (in accordance with ccitt rec. g.747 section 4). note that the ds2 framer is an off-line framer, indicating both off and cofa. error events continue to be indicated even when the frmr is indicating oof, based on the previous frame alignment. the red alarm and alarm indication signal are detected by the ds2 frmr in 9.9 ms for ds2 format and in 6.9 ms for g.747 format. the framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" ds2 m-frame or g.747 frame intervals. for the red alarm, a ds2 m-
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 79 frame (or g.747 frame, depending upon the framing format selected) is said to be a "valid" interval if it contains a red defect, defined as the occurrence of an oof event during that m-frame (or g.747 frame). for ais, a ds2 m-frame (or g.747 frame) is said to be a "valid" interval if it contains ais, defined as the occurrence of less than 9 zeros while the framer is out of frame during that m- frame (or g.747 frame). the discrepancy threshold ensures the detection algorithm operates in the presence of bit error rates of up to 10-3. each "valid" ds2 m-frame (or g.747 frame) causes an integration counter to increment; "non- valid" ds2 m-frame (or g.747 frame) intervals cause a decrement. red or ais is declared if the associated integrator count saturates at 53, resulting in a detection time of 9.9 ms for ds2 and 6.9 ms for g.747. red or ais declaration is deasserted when the associated count decrements to 0. the ds2 x-bit or g.747 remote alarm indication (rai) bit is extracted by the ds2 frmr to provide an indication of far end receive failure. the ferf status is set to the current x/rai state only if the two successive x/rai bits were in the same state. the extracted ferf status is buffered for 6 ds2 m-frames or 6 g.747 frames before being reported within the ds2 frmr status register. this buffer ensures a virtually 100% probability of freezing the ferf status in a valid state during an out of frame occurrence in ds2 mode, and ensures a better than 99.9% probability of freezing the valid st atus during an oof occurrence in g.747 mode. when an oof occurs, the ferf value is held at the state contained in the last buffer location corresponding to the previous sixth m-frame or g.747 frame. this location is not updated until the oof condition is deasserted. meanwhile, the last four of the remaining five buffer locations are loaded with the frozen ferf state while the first buffer location corresponding to the current m- frame/ g.747 frame is continually updated every m-frame/g.747 frame based on the above ferf definition. once correct frame alignment has been found and oof is deasserted, the first buffer location will contain a valid ferf status and the remaining five buffer locations are enabled to be updated every m-frame or g.747 frame. ds2 m-bit and f-bit framing errors are indicated as are g.747 framing word errors (or bit errors) and g.747 parity errors. these error indications are accumulated for performance monitoring purposes in internal, microprocessor readable counters. the performance monitoring accumulators continue to count error indication even while the framer is indicating oof. the ds2 frmr may be configured to generate interrupts on error events or status changes. all sources of interrupts can be masked or acknowledged via internal registers. internal registers are also used to configure the ds2 frmr.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 80 9.14 m12 multiplexer (mx12) the mx12 m12 multiplexer integrates circuitry required to asynchronously multiplex and demultiplex four ds1 streams into, and out of, an m12 formatted ds2 serial stream (as defined in ansi t1.107 section 7) and to support asynchronous multiplexing and demultiplexing of three 2048 kbit/s into and out of a g.747 formatted 6312 kbit/s high speed signal (as defined in ccitt rec. g.747). when multiplexing four ds1 streams into an m12 formatted ds2 stream, the mx12 tsb performs logical inversion on the second and fourth tributary streams. rate adaptation to the ds2 is performed by integral fifo buffers, controlled by timing circuitry. the fifo buffers accommodate in excess of 5.0 uipp of sinusoidal jitter on the ds1 clocks for all ji tter frequencies. x, f, m, and c bits are also generated and inserted by the timing circuitry. software control is provided to transmit far end receive failure (ferf) indications, ds2 ais, and ds1 payload loopback requests. the loopback request is coded by inverting one of the three c-bits (the default option is compatible with ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7).two diagnostic options are provided to invert the transmitted f or m bits. when demultiplexing four ds1 streams from an m12 formatted ds2, the mx12 performs bit destuffing via interpretation of the c-bits. the mx12 also detects and indicates ds1 payload loopback requests encoded in the c-bits. as per ansi t1.107 section 7.2.1.1 and tr-tsy-000009 section 3.7, the loopback command is identified as c3 being the inverse of c1 and c2. because tr-tsy- 000233 section 5.3.14.1 recommends compat ibility with non-compliant existing equipment, the two other loopback command po ssibilities are also supported. as per tr-tsy-000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has been absent for five successive m-frames. ds1 payload loopback can be activated or deactivated under software control. during payload loopback the ds1 str eam being looped back still continues unaffected in the demultiplex direction. the second and fourth demultiplexed ds1 streams are logically inverted, and all four demultiplexed ds1 streams can be replaced with ais on an individual basis. similar functionality supports ccitt recommendation g.747. the fifo is still required for rate adaptation. the frame alignment signal and parity bit are generated and inserted by the timing circuitry. software control is provided to transmit remote alarm indication (rai), high speed signal ais, and the reserved bit. a diagnostic option is provided to invert the transmitted frame alignment signal and parity bit.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 81 when demultiplexing three 2048 kbit/s streams from a g.747 formatted 6312 kbit/s stream, the mx12 performs bit destuffing via interpretation of the c-bits. tributary payload loopback can be activated or deactivated under software control. although no remote loopback request has been defined for g.747, inversion of the third c-bit triggers a loopback request detection indication in anticipation of recommendation g.747 refinement. all three demultiplexed 2048 kbit/s streams can be replaced with ais on an individual basis. 9.15 tributary payload processor (vtpp) the tributary payload processor (vtpp) processes the virtual tributaries within an sts-1, au3, or tug3. the vtpp can be configured to process either vt1.5s or vt2s within an sts-1 or either tu11s or tu12s within an au3 or tug3. the number of tributaries managed by each vtpp ranges from 21 (when configured to process all vt2s or equivalently all tu12s) to 28 (when configured to process all vt1.5s or equivalently all tu11s). the tributary payload processor is used in both the ingress and egress data paths. in the egress direction the pointer interpreter section of the vtpp can be bypassed on a per tributary basis to allow for pointer generator in the absence of valid pointers which is necessary when mapping floating transparent virtual tributaries from the sbi bus. 9.15.1 clock generator the clock generator derives various clocks from the 19.44 mhz system clock and distributes them to other blocks within the tributary payl oad processor. the overall design is totally synchronous, with processing occurring at a 6.48 mhz rate in each tributary payload processor. 9.15.2 incoming timing generator the incoming timing generator identifies the incoming tributary being processed at any given point in time. based on the configuration of the vtpp (it can process various mixes of tributary types), the incoming timing generator extracts the sts-1 spe, vc3, or a single tug3 from a vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and those that carry specific tributaries to be processed. the h4 byte is identified for the incoming multiframe detector so that it can determine the incoming tributary multiframe boundaries. the identification of specific tributaries allows the pointer interpreter to be time-sliced across the mix of tributaries present in the incoming data stream. the identification of the v1-v3 bytes of vts, or tus allows the pointer interpreter to function.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 82 9.15.3 incoming multiframe detector the multiframe alignment sequence in the path overhead h4 byte is monitored for the bit patterns of 00, 01, 10, 11 in the two least significant bits. if an unexpected value is detected, the primar y multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift. the primary process will enter out of multiframe state (oom). a new multiframe alignment is chosen, and oom state is exited when four consecutive correct multiframe patterns are detected. loss of multiframe (lom) is declared after residing in the oom state at the ninth h4 byte without re-alignment. in counting to nine, the out of sequence h4 byte that triggered the transition to the oom state is counted as the first. a new multiframe alignment is chosen, and lom state is exited when four consecutive correct multiframe patterns are detected. changes in multiframe alignments are detected and reported. 9.15.4 pointer interpreter the pointer interpreter is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram as directed by the incoming timing generator. the pointer interpreter processes the incoming tributary pointers such that all bytes within the tributary synchronous payload envelope can be identified and written into the unique payload first-in first-out buffer for the tributary in question. a marker that tags the v5 byte is passed through the payload buffer. the incoming timing generator directs the pointer interpreter to the correct payload buffer for the tributary being processed. the pointer interpreter processes the incoming pointers (v1/v2) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5) in the incoming tug3 or sts-1 (au3) stream. 9.15.5 payload buffer the payload buffer is a bank of fifo buffers. it is synchronous in operation and is based on a time-sliced ram. the three 19.44 mhz clock cycles in each 6.48 mhz period are shared between the read and write operations. the pointer interpreter writes tributary payload data and the v5 tag into the payload buffer. a 16 byte fifo buffer is provided for each of the (up to 28) tributaries. address information is also passed through the payl oad buffer to allow fifo fill status to be determined by the pointer generator. 9.15.6 outgoing timing generator the outgoing timing generator identifies the outgoing tributary byte being processed. based on the configuration of the vtpp, the outgoing timing
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 83 generator effectively constructs the sts-1 spe, vc3, or vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and bytes that carry specific tributaries. the identification of specific tributaries allows the pointer generator to be time-sliced across the mix of tributaries to be sourced in the outgoing data stream. the identification of the v1-v3 bytes of vts, or tus allows the pointer generator to function. the sequence of h4 bytes is generated by each tributary payload processor and inserted into the outgoing administrative units. the six most significant bits of h4 are set to logic 1. the sequence of the remaining two h4 bits is determined by the multiframe alignment. 9.15.7 pointer generator the pointer generator block generates the tributary pointers (v1/v2) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5) on the outgoing stream. the pointer generator is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram at the address associated with the current tributary. the pointer generator fills the outgoing tributary synchronous payload envelopes with bytes read from the associated fifo in the payload buffer for the current tributary. the pointer generator creates pointers in the v1-v3 bytes of the outgoing data stream. the marker that tags the v5 byte that is passed through the payload buffer is used to align the pointer. the outgoing timing generator directs the pointer generator to the fifo in the payload buffer that is associated with the tributary being processed. the pointer generator monitors the fill levels of the payload buffers and inserts outgoing pointer justifications as necessary to avoid fifo spillage. normally, the pointer generator has a fifo dead band of two bytes. the dead band can be collapse to one so that any incoming pointer justifications will be reflected by a corresponding outgoing justification with no attenuation. signals are output by the pointer generator that identify outgoing v5 bytes and the tributary synchronous payload envelopes. on a per tributary basis, tributary path ais and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. the idle code is selectable globally for the entire vc3 or tug3 to be all-zeros or all-ones. it is also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. tributary path ais is automatically inserted into outgoing tributaries if the pointer interpreter detects tributary path ais on the corresponding incoming tributary.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 84 9.16 receive tributary path overhead processor (rtop) the tributary path overhead processor (rtop) monitors the outgoing stream of the tributary payload processor (vtpp) and processes the tributaries within an sts-1, au3, or tug3. the rtop can be configured to process all the vt1.5s or vt2s that can be carried in an sts-1 or all the tu11s or tu12s that can be carried in an au3 or tug3. the number of tributaries managed by each rtop ranges from 21 (when configured to process all vt2s or all tu12s) to 28 (when configured to process all vt1.5s or all tu11s). the rtop provides tributary performance monitoring of incoming tributaries. bit interleaved parity of the incoming tributaries is computed and compared with the bip-2 code encoded in the v5 byte of the tributary. errors between the computed and received values are accumulated. rtop also accumulates far end block error codes. incoming path signal label is debounced and compared with the provisioned value. path signal label unstable, path signal label mismatch and change of path signal label event are identified. 9.16.1 clock generator the clock generator derives a 6.48 mhz clock from the 19.44 mhz system clock and distributes this to the tributary payload processor. 9.16.2 timing generator the timing generator identifies the incoming tributary being processed at any given point in time. based on the configuration of the rtop (it can process various mixes of tributary types), the incoming timing generator extracts the sts- 1 spe, vc3, or a single tug3 from a vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and those that carry specific tributaries to be processed. the identification of specific tributaries allows the error monitor and extract bl ocks to be time-sliced across the mix of tributaries present in the incoming data stream. 9.16.3 error monitor the error monitor block is a time-sliced state machine. it relies on the timing generator block to identify the tributary being processed. the error monitor block contains a set of 12-bit counters that are used to accumulate tributary path bip-2 errors, and a set of 11-bit counters to accumulate far end block errors (febe). the contents of the counters may be transferred to a holding ram, and the counters reset under microprocessor control.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 85 tributary path bip-2 errors are detected by comparing the tributary path bip-2 bits in the v5 byte extracted from the current multiframe, to the bip-2 value computed for the previous multiframe. bip-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. far end block errors (febes) are detected by extracting the febe bit from the tributary path overhead byte (v5). tributary path remote defect indication (rdi) and remote failure indication (rfi) are detected by extracting bit 8 and bit 4 respectively of the tributary path overhead byte (v5). the rdi is recognized when bit 8 of the v5 byte is set high for five or ten consecutive multiframes while rfi is recognized when bit 4 of v5 is set high for five or ten consecutive frames. the rdi and rfi bits may be treated as a two-bit code word. a code change is only recognized when the code is unchanged for five or ten frames. the tributary path signal label (psl) found in the tributary path overhead byte (v5) is processed. an incoming psl is accepted when it is received unchanged for five consecutive multiframes. the accepted psl is compared with the associated provisioned value. the psl match/mismatch state and uneq (unequipped) state is determined by the following: table 2 - path signal label mismatch state expected psl accepted psl pslm state uneq state (unequipped) 000 000 match inactive 000 001 mismatch inactive 000 pdi code mismatch inactive 000 xxx 000, 001, pdi code mismatch inactive 001 000 mismatch active (unequipped) 001 001 match inactive 001 pdi code match inactive 001 xxx 000, 001, pdi code match inactive pdi code 000 mismatch active (unequipped) pdi code 001 match inactive pdi code pdi code match inactive pdi code xxx 000, 001, pdi code mismatch inactive
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 86 expected psl accepted psl pslm state uneq state (unequipped) xxx 000, 001, pdi code 000 mismatch active (unequipped) xxx 000, 001, pdi code 001 match inactive xxx 000, 001, pdi code xxx match inactive xxx 000, 001, pdi code yyy mismatch inactive each time an incoming psl differs from the one in the previous multiframe, the psl unstable counter is incremented. thus, a single bit error in the psl in a sequence of constant psl values will caus e the counter to increment twice, once on the errored psl and again on the first error-free psl. the incoming psl is considered unstable when the counter r eaches five. the counter is cleared when the same psl is received for five consecutive multiframes. 9.17 receive tributary demapper (rtdm) the receive tributary demapper (rtdm) demaps up to 28 t1 or 21 e1 bit asynchronous mapped signals from an sts-1 spe, tug3 within a stm-1/vc4 or stm-1 vc3 payload. the bit asynchronous t1 mapping consists of 104 octets every 500 s (2 khz) and is shown in table 3. the bit asynchronous e1 mapping consists of 140 octets every 500us and is shown in table 4. table 3 - asynchronous t1 tributary mapping v5 rrrrrrir 24 bytes - 8i j2 c 1 c 2 ooooir 24 bytes - 8i z6 c 1 c 2 ooooir 24 bytes - 8i z7
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 87 v5 c 1 c 2 rrrs 1 s 2 r 24 bytes - 8i r: fixed stuff bit - set to logic ?0? or ?1? c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead i: t1 payload information table 4 - asynchronous e1 tributary mapping v5 r 32 bytes - 8i r j2 c 1 c 2 oooorr 32 bytes ? 8i r z6 c 1 c 2 oooorr 32 bytes ? 8i r z7 c 1 c 2 rrrrrs 1 s 2 i i i i i i i 31 bytes ? 8i r r: fixed stuff bit - set to logic ?0? or ?1?
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 88 c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead i: e1 payload information the rtdm buffers the tributary synchronous payload envelope bytes of the incoming tributaries in individual fifos to accommodate tributary pointer justifications. the rtdm performs majority voting on the tributary stuff control (c1, c2) bits. if the majority of each set of the stuff control bits indicate a stuff operation, then the associated stuff opportunity bit (s1, s2 ) will not carry t1 or e1 payload. conversely, if the majority of the stuff control bits indicate a data operation, the appropriate stuff opportunity bit(s) will carry t1 or e1 payload. at each multiframe boundary, the rtdm indicates to the down stream parallel to serial converter (piso) the status of the stuff control bits. for t1 streams, the parallel to serial converter can be controlled to generate 771, 772 or 773 t1 clock cycles. for e1 streams, the number of clock cycles is controllable to 1023, 1024 or 1025. the rtdm attenuates jitter introduced by pointer justification events. tributary payload data is held in a fifo. when a pointer justification is detected, the rtdm issues evenly spaced commands to the down stream parallel to serial converter block which makes 1/12 ui adjustments to the phase of its generated t1 output clock or 1/9 ui adjustments to the e1 clock. the number of commands sent per incoming pointer justification is based on the observation that four t1 or e1 frames are delivered or deleted for each full round of 104 vt1.5 (tu-11) or 140 vt2 (tu-12) pointer justifications. 9.18 parallel in to serial out converter (piso) the parallel in to serial out converter (piso) serializes up to 28 t1 or 21 e1 tributaries which have been demapped from the sts-1 spe or stm-1au3 or vc3 via the receive tributary demapper (rtdm). in conjunction with the receive tributary demapper (rtdm) this block performs the desynchronizer function to provide a low jitter t1 or e1 serial clock and data. the desynchronizer uses a combination of two clock generation techniques to desynchronize the demapped t1s and e1s. incoming bit stuff events cause an extra bit of data to be generated or removed from the generated serial stream over the following 2khz multi-frame. pointer justifications are spread out by advancing or retarding the generated t1 or e1 clock phase.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 89 the 19.44mhz lrefclk input is used to generate a nominal 1.544mb/s or 2.048mb/s clock over a 2khz interval as indicated by the ldc1j1v1 input divided by four. a nominal t1 rate consis ts of 772 clocks in 500us. a nominal e1 rate consists of 1024 clocks in 500us. stuf f events, as indicated by the rtdm block, are compensated within the desynchronizer by generating three separate clocks to construct the fa ster or slower rate as shown in table 5. a mixture of t1 clock cycles is generated using 12 refclk cycles (fast t1 cycles) and 13 refclk cycles (slow t1 cycles) to produce an overall rate of 1.544mhz over the 500us period. a mixture of e1 clock cycles is generated using 9 refclk cycles (fast e1 cycles) and 10 refclk cycles (slow e1 cycles) to produce an overall rate of 2.048mhz over the 500us period. table 5 shows the number of fast and slow cycles required to generate all three t1 and e1 rates. table 5 - desynchronizer clock generation algorithm clock rate fast t1 cycles slow t1 cycles overall t1 cycles fast e1 cycles slow e1 cycles overall e1 cycles slow 303 468 771 510 513 1023 nominal 316 456 772 520 504 1024 fast 329 444 773 530 495 1025 pointer justification events, as indicated by the rtdm block, are compensated within the desynchronizer by advancing or retarding the phase of the generated fast, slow and nominal cl ocks during the 2khz peri od. because pointer justification have a limited frequency of occurrence the phase adjustments are leaked out slowly. twelve phase adjustments will remove or add an entire t1 clock whereas nine phase adj ustments will remove or add an entire e1 clock. the number of phase adjustments needed per pointer justification is on average 89.077 for t1 or 65.829 for e1. these pointer adjustments are spread out over a 1 second period. 9.19 ds3 mapper drop side (d3md) the ds3 mapper drop side (d3md) block demaps a ds3 signal from an sts-1 (stm-0/au3) payload. the asynchronous ds3 mapping consists of 9 rows every 125 s (8 khz). each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. fixed stuff bytes are used to fill the re maining bytes. the asynchronous ds3 mapping is shown in table 6.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 90 table 6 - asynchronous ds3 ma pping to sts-1 (stm-0/au3) j1 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i sts 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i poh 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i r: fixed stuff bit - set to logic ?0? or ?1? c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead communication channel i: ds3 payload information 9.19.1 ds3 demapper the d3md performs majority vote on the received c-bits. if 3 out of 5 c-bits are ?1?s, the associated s bit is interpreted as a stuff bit. if 3 out of 5 c-bits are ?0?s, the associated s bit is interpreted as an information bit. the information bits are written to an elastic store and the fixed stuff bits (r) are ignored. given a path signal label mismatch (pslm) or path signal label unstable (pslu), the d3md ignores the sts-1 (stm-0/au3) spe and writes a ds3 ais pattern to the elastic store. in addition, the desynchronization algorithm assumes a nominal ratio of data to stuff bits carried in the s bits (1 out of 3 s bits is assumed to be an information (data) bit). ds3 ais is shown in table 7. table 7 - ds3 ais format. x (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d x (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d p (p) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d p (p) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (0) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 91 x (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (0) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d valid m-frame alignment bits (m-bits), m-subframe alignment bits (f-bits), and parity bit of the preceding m-frame (p-bits). the two p-bits are identical, either both are zeros or ones. all the c-bits in the m-frame are set to zeros the x-bits are set to ones the information bit (84 data bits with repeating sequence of 1010..) 9.19.2 ds3 demapper elastic store the elastic store block is provided to compensate for frequency differences between the ds-3 stream extracted from the sts-1 (stm-0/au3) spe and the incoming clk52m. the ds3 demapper extracts i bits from the sts-1 (stm-0/au3) spe and writes the bits into a 128 bit (16 byte) elastic store. eight bytes are provided for sonet/sdh overhead (3 bytes for toh, 1 byte for a positive stuff, 1 byte for poh) and ds3 reserve stuffing bits (2 bytes for r bits, and 3 overhead bits which is rounded-up to 1 byte). the remaining 8 bytes are provided for path pointer adjustments. data is read out of the elastic store using a divide by 8 version of the input clk52m clock. if an overflow or underflow condition occurs, an interrupt is optionally asserted and the elastic store read and write address are reset to the startup values (logically 180 degrees apart). 9.19.3 ds3 desynchronizer the desynchronizer monitors the elastic store level to control the de-stuffing algorithm to avoid overflow and underflow conditions. the desynchronizer assumes either a 51.84 mhz clock (provided internally) or a 44.928 mhz clock (provided via input clk52m). when using a 44.928 mhz clk52m clock, the ds3 clock is generated using a fixed 8 khz interval. the 8khz interval is subdivided into 9 rows. each row contains either 621 or 622 clock periods. the ds3riclk contains 624 pulses at 72khz (9*8khz). to generate 621 pulses, a gap pattern of 207 clocks + 1 clock
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 92 gap + 207 clocks + 1 clock gap + 207 clocks + 1 clock gap is used. to generate 622 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 208 clocks is used. when using a 51.84 mhz clk52m clock, the ds3 clock is generated using similar gapping patterns. to generate 621 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 36 * (5 clo cks + 1 clock gap) is used. to generate 622 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 35 * (5 clocks + 1 clock gap) + 6 clocks is used. table 8 illustrates the gap patterns us ed to generate the desynchronized ds3 clock under the normal, ds3 ais, faster and slower status. the faster pattern is used to drain the elastic store to avoid overflows. the slower pattern is used to allow the elastic store to fill to avoid underflows. table 8 - ds3 desynchronizer clock gapping algorithm. row number normal or ds3 ais run faster run slower 1 621 621 621 2 621 621 621 3 622 622 622 4 621 621 621 5 621 622 621 6 622 622 621 7 621 621 621 8 621 622 621 9 622 622 621 9.20 transmit tributary path overhead processor (ttop) the transmit tributary path overhead processor (ttop) generates the path overhead for up to 28 vt1.5/tu-11s or 21 vt2/tu-12s. when configured for sonet compatible operation, the ttop inserts the four tributary path overhead bytes (v5, j2, z6, and z7) to each tributary. the ttop may also be configured for sdh compatible operation. the incoming stm-1 stream may carry three au3s or an au4 with three tug3s. the ttop computes the bip-2 code in the current tributary spe and inserts the result into the bip-2 bits of the v5 byte in the next tributary spe. the tributary
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 93 path signal label in the v5 byte of each tributary can be sourced from internal registers. the tributary far end block error bit in the v5 byte of each tributary is inserted based of the bip error count detected at a companion rtop tsb. the tributary remote failure indication and remote defect indication bits in the v5 or the z7 byte of each tributary is inserted based on the tributary alarm status from the companion tributary remote alarm processor, trap, tsb. the ttop inserts the tributary trail trace identifier into the j2 byte. each tributary is provided with a 64-byte buffer to store the identifier. one shadow buffer is available for temporary replacement of a selected transmitted tti while the 64-byte identifier buffer is being updated. data is retrieved sequentially from the active buffer at each j2 byte position. the shadow buffer can be programmed with new messages without timing constraints when inactive. an inactive 64-byte identifier buffer can also be programmed with new messages without timing constraints. programming for tti buffers is done one buffer at a time by first programming the shadow buffer, switching to the shadow buffer for the desired tributary, updating the desired tributary identifier buffer and finally switching back from the shadow buffer to the tributary buffer. switching between the shadow buffer and normal buffer is synchronized to the start of each identifier on a per-tributary basis. 9.21 transmit remote alarm processor (trap) when configured for sonet compatible operation, the trap sonet/sdh transmit remote alarm processor processes remote alarm indications of tributaries in an sts-3 stream. the virtual tributaries within an sts-1 stream may be configured to accept either vt1.5 or vt2 tributary types. the trap may also be configured for sdh compatible operation. the incoming stm-1 stream may carry three au3s or an au4 with three tug3s. the trap may be configured to insert tributary remote defect indications (rdi-v) and tributary remote error indications (rei-v) via the ttop block. these indications may originate from three sources: (1) based on alarms detected in tributaries received on the telecom drop bus, lddata[7:0]. the exact behavior is configured using the sonet/sdh master tributrary remote defect indication control register and the sonet/sdh master tributary au xiliary remote defect indication register. (2) based on two independent serial alarm ports, radeast and radwest. rei indications are generated based on the sampled bip-2 error values. rdi indications are based on the sampled rdi (remote defect indication) and rfi (auxiliary remote defect indication) values.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 94 (3) using the forceen feature in the trap control registers to manually force desired values using the rdi (remote defect indication) and rfi (auxiliary remote defect indication) bits. the source of alarm status can be conf igured on a per-tributary basis. as well, alarm information from tributaries in any of the three sources of remote alarms can be mapped to arbitrary tributaries in the outgoing data stream via the indirect remote alarm tributary register and the indirect datapath tributary register of the trap block. two methods of encoding tributary remote alarms are supported: non-extended rdi and extended rdi. this selection is made on a per-tributary basis by setting the erdi bits of the trap control registers and the ttop control registers. in non-extended rdi mode, rdi indications are encoded as a one bit value (rdi, remote defect indication) reflected in the v5 byte of the outgoing tributrary path overhead. in extended rdi mode, rdi indications are encoded as a two bit value (rdi, remote defe ct indication and rfi, auxiliary remote defect indication), and are reflected in both the v5 byte and z7 byte of the outgoing tributary path overhead. specifically, the outgoing path overhead bits are mapped as follows: path overhead bits non-extended rdi (erdi=0) extended rdi (erdi=1) v5 bit 3 rei rei v5 bit 8 rdi rdi z7 bit 5 0 rdi z7 bit 6 0 rfi z7 bit 7 0 not(rfi) in all cases, the rdi-v state will be sent for a minimum of 10 multiframes before changing, unless a higher priority alarm is required. 9.22 transmit tributary mapper (ttmp) the transmit tributary mapper block bit asynchronously maps up to 28 t1 or 21 e1 streams into an sts-1 spe, tug3 in a stm-1/vc4 or stm-1/vc3 payload. the ttmp compensates for any frequency differences between the incoming
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 95 individual serial bit rates and the available sts-1 or stm-1/vc3 payload capacity. the asynchronous t1 mapping consists of 104 octets every 500 s (2 khz). the asynchronous e1 mapping consists of 140 octets every 500 s (2 khz). refer to the rtdm block for a description of the asynchronous t1 and e1 mappings. the tributary mapper is a time-sliced state machine which uses a payload buffer as an elastic store. the t1 or e1 streams are read from the payload buffer, and mapped into vt1.5 payloads and vt2 payloads using bit asynchronous mapping only. the tributary mapper compensates for phase and frequency offsets using bit stuffing. a jitter-reducing control loop is used to monitor the payload buffer depth and reduce mapping jitter to 1.0 ui. to reduce mapping jitter even further, a dither technique is inserted between the control loop and the stuff bit generator resulting in an acceptable desynchronizer mapping jitter of about 0.3 ui. the tributary mapper may optionally act as a time switch. when time switch enable is active, the association of tributary mapper vt payloads to logical fifo data streams is software configurable. there are two pages in the time switch configuration ram. one page is software selectable to be the active page and the other the stand-by page. the configuration in the active page is used to associate outgoing vt payloads to logical fifos. the stand-by page can be programmed to the next switch configuration. change of page selection is synchronized to incoming stream frame boundaries. when time switch enable is inactive, the association of outgoing vt payloads to logical fifos is fixed. the ttmp outputs the sts-1, tug3 in a stm-1/vc4 or stm-1/vc3 with the bit asynchronous mapped t1s or e1s onto an internal bus for further processing by the transmit tributary payload processor block. 9.23 serial in to parallel out converter (sipo) the serial in to parallel out converter (sipo) accepts serial data from up to 28 t1 or 21 e1 sources and converts these streams to byte serial format. the bytes are passed to the transmit tributary mapper (ttmp) for bit asynchronous mapping into the sts-1. 9.24 ds3 mapper add side (d3ma) the ds3 mapper add side (d3ma) block maps a ds3 signal into an sts-1 (stm-0/au3) payload and compensate for any frequency differences between the incoming ds3 serial bit rate (ticlk) and the available sts-1 (stm-0/au3) spe mapped payload capacity. the asynchronous ds3 mapping consists of 9 rows every 125 s (8 khz). each row contains 621 information bits, 5 stuff
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 96 control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. fixed stuff bytes are used to fill the remaining bytes. please refer to section 9.19 for a description of the ds3 mapping. 9.24.1 ds3 mapper serializer high speed serial data from the ds3-tran block is deserialized and written into the elastic store. 9.24.2 ds3 mapper elastic store the elastic store block is provided to compensate for frequency differences between the ds3 stream from the ds3-tran block and the sts-1 (stm-0/au3) spe capacity. the ds3 serializer writes data into the elastic store at the ticlk/8 rate while data is read out at the stuffed sts-1 (stm-0/au3) byte rate. if an overflow or underflow condition occurs, an interrupt is optionally asserted and the elastic store read and write address are reset to the startup values (logically 180 degrees apart). the elastic store is 128 bits (16 bytes) to allow for a fixed read/write pointer lag of 7 bytes (3 bytes for toh, 1 byte for poh, 2 bytes for r bits, and 3 overhead bits which is rounded-up to 1 byte). four bytes are also added on either side for positive and negative threshold detection. 9.24.3 ds3 synchronizer the ds3 synchronizer performs the mapping of the ds3 into the sts-1 (stm-0/au3) spe. the ds3 synchronizer monitors the elastic store level to control the stuffing algorithm to avoid overflow (i.e. run faster) and underflow (i.e. run slower) conditions. the fill leve l of the elastic stor e is monitored and stuff opportunities in the ds3 mapping are used to center the elastic store. to consume a stuff opportunity, the five c-bits on a row are set to ones and the s bit is used to carry an ds3 information bit. when the s bit is not used to carry information, the c-bits on the row are set to zeros. the ds3 synchronizer uses a fixed bit leaking algorithm which leaks 8 bits of phase buildup in 500 s. the 8khz sts-1 (stm-0/au3) frame interval is subdivided into 9 rows. each row contains one stuff opportunity. table 9 illustrates the stuffing implementation where s means stuff bit and i means an information bit (ds3 data).
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 97 table 9 - ds3 synchronizer bit stuffing algorithm. row number normal or ds3 ais run faster run slower 1 s s s 2 s s s 3 i i i 4 s s s 5 s i s 6 i i s 7 s s s 8 s i s 9 i i s under microprocessor control, the incoming ds3 stream can be overwritten with the framed ds3 ais. when asserting ds3 ais, a nominal stuff pattern is used as illustrated above. please refer to t he d3md functional de scription section for a description of the ds3 ais frame. the d3ma outputs the sts-1 (stm-0/au3) with the mapped ds3 onto the line add bus, ladata[7:0]. 9.25 egress system interface (esif) the egress system interface (esif) block provides system side serial clock and data access for up to 28 t1 or 21 e1 transmit streams. control of the system side interface is global to temap and is selected through the sysopt[2:0] bits in the global configuration register at address 0001h. the system interface options are serial clock and data or sbi bus. there are two serial clock and data egress interface modes provided by temap, clock master: clear channel and clock slave: clear channel. the egress serial clock and data interface clocking modes are selected via the emode[2:0] bits in the t1/e1 egress serial interface mode select register. in all egress clock master modes the transmit clock can be sourced from either the common transmit clock, ctclk, one of the two recovered clocks, recvclk1 and recvclk2, or the received clock for that link. the selection between ctclk, recvclk1 and recvclk2 as the reference transmit clock is the same for all t1/e1 framers. jitter attenuation can be applied to the master mode clock with the tjat.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 98 figure 14 - clock master: clear channel esif egress system interface transmitter ed[1:28] eclk[1:28] tjat digital pll ed[x] timed to eclk[x] transmit data[1:28] transmit clk[1:28] ctclk receive clk[1:28] clock master: clear channel mode has no frame alignment therefore no frame alignment is indicated to the upstream device. eclk[x] is a continuous clock at 1.544mb/s for t1 links or 2.048mb/s for e1 links. figure 15 - clock slave: clear channel tjat fifo esif egress system interface transmitter transmit data[1:28] ed[1:28] eclk[1:28] tjat digital pll transmit clk[1:28] input timed to eclk[x] in clock slave: clear channel mode, the egress interface is clocked by the externally provided egress clock, eclk[x]. eclk[x] must be a 1.544 mhz clock for t1 links or a 2.048 mhz clock for e1 links. in this mode the t1/e1 framers are bypassed except for the tjat which may or may not be bypassed depending on the setting of the tjatbyp bit in the t1/e1 egress line interface options register. typically the tjat would be bypassed unless jitter attenuation is required on eclk[x]. 9.26 ingress system interface (isif) the ingress system interface (isif) block provides a system side clock master serial clock and data access for up to 28 t1 or 21 e1 clear channel receive streams. control of the system side interface is global to temap and is selected through the sysopt[2:0] bits in the global configuration register at address 0001h. the system interface options are serial clock and data or sbi bus.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 99 the ingress clock master: clear channel interface mode is selected via the imode[1:0] bits in the t1/e1 ingress serial interface mode select register. figure 16 - clock master: clear channel isi f ingress syst em inte rfac e receiver id[1 :28] iclk[ 1:28] id[x]timed to ic lk [x] rjat digita l jitter a ttenuato r receive clk[1:28] receive data[1:28] in clock master: clear channel mode, the ingress clock (iclk[x]) is a jitter attenuated version of the 1.544 mhz or 2.048 mhz receive clock coming from either the m13 multiplex or sonet/sdh demapper. the ingress data appears on id[x]. 9.27 extract scaleable bandwidth interconnect (exsbi) the extract scaleable bandwidth interconnect block demaps up to 28 1.544mb/s links, 21 2.048mb/s links or a single 44.736mb/s link from the sbi shared bus. the 1.544mb/s links can be unframed when used in a straight multiplexer or mapper application, or they can be t1 framed and channelized for insertion into the ds3 multiplex or sonet/sdh mapping. the 2.048mb/s links can be unframed when used in a straight mapper application, or they can be e1 framed and channelized for insertion into the sonet/sdh mapping. the 44.736mb/s link can also be unframed for mapping into sonet/sdh or it can be ds3 unchannelized when the temap is used as a ds3 framer. all egress links extracted from the sbi bus can be timed from the source or from the temap. when timing is from the source the exsbi commands the piso to generate 1.544mb/s, 2.048mb/ s or 44.736mb/s clocks slaved to the arrival rate of the data or from timing link rate adjustments provided from the source and carried with the links over the sbi bus. the 1.544mb/s clock is synthesized from the 19.44mhz reference clock, srefclk, by dividing the clock by either 12 or 13 in a fixed sequence that produces the nominal 1.544mb/s rate. the 2.048mb/s clock is synthesized from the 19.44mhz reference clock by dividing the clock by either 9 or 10 in a fixed sequence that produces the nominal 2.048mb/s rate. timing adjustments are made over 500us intervals and are done by either advancing or retarding the phase or by adding or deleting a whole 1.544mb/s or 2.048mb/s clock cycle over the 500us period.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 100 the 44.736mb/s clock is synthesized from the 51.84mhz or 44.928mhz reference clock, clk52m. using either reference clock frequency, the 44.736mb/s rate is generated by gapping the reference clock in a fixed way. timing adjustments are perfo rmed by adding or deletin g four clocks over the 500us period. when the temap is the sbi egress clock master for a link, clocks are sourced within the temap. based on buffer fill levels, the exsbi sends link rate adjustment commands to the link source indicating that it should send one additional or one fewer bytes of data during the next 500us interval. failure of the source to respond to these commands w ill ultimately result in overflows or underflows which can be configured to generate per link interrupts. 9.28 insert scaleable bandwidth interconnect (insbi) the insert scaleable bandwidth interconnect block maps up to 28 1.544mb/s links, 21 2.048mb/s links or a single 44.736mb/s link into the sbi shared bus. the 1.544mb/s links can be unframed when sourced directly from the ds3 multiplexer or sonet/sdh mapper, or they can be t1 channelized when sourced by the t1 framers. the 2.048mb/s links can be unframed when sourced directly from the sonet/sdh mapper, or they can be e1 channelized when sourced by the e1 framers. the 44.736mb/s link can also be unframed when sourced directly from the ds3 interface or from the ds3 mapper. the 44.736mb/s link can be an unchannelized ds3 when sourced from the ds3 framer. links inserted into the sbi bus can be timed from the temap or from the far end. the insbi makes link rate adjustments by adding or deleting an extra byte of data over a 500us interval based on buffer fill levels. timing adjustments made by the insbi are detected by the receiving sbi interface by explicit signals in the sbi bus structure. the insbi optionally sends link rate information across the sbi bus. this information is used by the receiving sbi interface to create a recovered link clock which is based on small clock phase adjustments signaled by the insbi. 9.29 scaleable bandwidth interconnect piso (sbipiso) the scaleable bandwidth interconnect parallel to serial converter (sbipiso) generates up to 28 t1s, 21 e1s or a ds3 serial clock and data signals from the byte serial stream provided by the extract sbi block. the generated clock rate can be controlled with commands from the exsbi. in clock slave mode the generated clock will be increased or dec reased in small increments based on fifo fill levels within the exsbi or directly with clock rate commands from the far end device who is mastering the clock across the sbi bus. in clock master mode
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 101 the sbipiso controls the bit rate by accepting data from the exsbi at the rate of the individual t1, e1 or ds 3 clocks sourced into it. in addition the sbipiso generates frame pulses and multiframe pulses for all t1s, e1s and ds3. 9.30 scaleable bandwidth interconnect sipo (sbisipo) the scaleable bandwidth interconnect serial to parallel converter (sbisipo) sinks up to 28 t1s, 21 e1s or a ds3 serial clock and data signals and generates a byte serial stream to the insert sbi block. the sbisipo measures the serial clock against the sbi reference clock and sends this information to the insbi block and in turn across the sbi bus to the clock generation slave, sbipiso. in this way an accurate representation of the input clock rate is communicated across the sbi bus. in addition the sbisipo generates byte serial streams from frame pulses and multiframe pulses for all t1s, e1s and ds3. 9.31 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. the temap identification code is 553650cd hexadecimal. 9.32 microprocessor interface the microprocessor interface block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the temap. the register memory map in table 10 shows where the normal mode registers are accessed. the registers are organized so that backward software compatibility with existing pmc devices is optimized. the resulting register organization splits into sections: master configuration registers, 28 sets of t1/e1 framer registers, ds3 m13 multiplexing registers, sonet/sdh mapping registers and sbi registers. on power up reset the temap defaults to 28 t1 framers multiplexed into the m13 multiplexer using the ds3 m23 multiplex format. for proper operation some register configuration is necessary. system side access defaults to the sbi bus without any tributaries enabled which will leave the sbi drop bus tristated. by default interrupts will not be enabled, automat ic alarm generati on is disabled, a
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 102 dual rail ds3 liu interface is expected and an external transmit reference clock is required. table 10 - register memory map address register 0000h global reset 0001h global configuration 0002h revision/global pmon update 0003h master recovered clock#1/reference clock select 0004h recovered clock#2 select 0005h- 000fh reserved 00010h master clock monitor #1 0011h master clock monitor #2 0012h master clock monitor #3 0013h master clock monitor #4 0014h master clock monitor #5 0015h- 001fh reserved 0020h master interrupt source 0021h master interrupt status t1/e1 #1-8 0022h master interrupt status t1/e1 #9-16 0023h master interrupt status t1/e1 #17-24 0024h master interrupt status t1 #25-28 0025h master interrupt status sdh 0026h master interrupt status source sbi 0027h reserved 0028h master interrupt status ds3 0029h master interrupt status ds2 002ah master interrupt status mx12 002bh reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 103 address register 002ch master sbidet0 collision detect lsb 002dh master sbidet0 collision detect msb 002eh master sbidet1 collision detect lsb 002fh master sbidet1 collision detect msb 0030h- 007fh reserved 0080h- 00ffh t1/e1 pmon #1 0080h t1/e1 master configuration 0081h reserved 0082h t1/e1 receive options 0083h t1/e1 alarm configuration 0084h t1/e1 egress line interface configuration 0085h t1/e1 master ingress serial interface mode select 0086h t1/e1 master egress serial interface mode select 0087h- 0088h reserved 0089h t1/e1 master serial interface configuration 008ah reserved 008bh t1/e1 interrupt source #1 008ch t1/e1 interrupt source #2 008dh t1/e1 diagnostics 008eh t1/e1 prbs positioning and hdlc control 008fh reserved 0090h rjat interrupt status 0091h rjat reference clock divisor n1 control 0092h rjat output clock divisor n2 control 0093h rjat configuration 0094h tjat interrupt status
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 104 address register 0095h tjat reference clock divisor n1 control 0096h tjat output clock divisor n2 control 0097h tjat configuration 0098h- 00b7h reserved 00b8h pmon interrupt enable/status 00b9h pmon framing bit error count 00bah pmon oof/cofa/far end block error count (lsb) 00bbh pmon oof/cofa/far end block error count (msb) 00bch pmon bit error/crce count (lsb) 00bdh pmon bit error/crce count (msb) 00beh pmon reserved 00bfh pmon reserved 00c0h- 00cfh reserved 00d0h prbs generator/checker control 00d1h prbs checker interrupt enable/status 00d2h prbs pattern select 00d3h prbs reserved 00d4h prbs error count register #1 00d5h prbs error count register #2 00d6h prbs error count register #3 00d7h prbs reserved 00d8h- 00dfh reserved 00e0h t1 almi configuration 00e1h t1 almi interrupt enable 00e2h t1 almi interrupt status 00e3h t1 almi alarm detection status
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 105 address register 00e4h- 00ebh reserved 00ech t1 frmr configuration 00edh t1 frmr interrupt enable 00eeh t1 frmr interrupt status 00efh t1 frmr reserved 00f0h- 00ffh reserved 00e0h e1 frmr frame alignment options 00e1h e1 frmr maintenance mode options 00e2h e1 frmr framing status interrupt enable 00e3h e1 frmr maintenance/alarm status interrupt enable 00e4h e1 frmr framing status interrupt indication 00e5h e1 frmr maintenance/alarm status interrupt indication 00e6h e1 frmr framing status 00e7h e1 frmr maintenance/alarm status 00e8h e1 frmr international/national bits 00e9h e1 frmr crc error count - lsb 00eah e1 frmr crc error count - msb 00ebh e1 frmr national bit codeword interrupt enables 00ech e1 frmr national bit codeword interrupts 00edh e1 frmr national bit codewords 00eeh e1 frmr frame pulse/alarm interrupt enables 00efh e1 frmr frame pulse/alarm interrupt 00f0h- 00ffh reserved 0100h- 017fh t1/e1 pmon slice #2 0180h- 01ffh t1/e1 pmon slice #3
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 106 address register 0200h- 027fh t1/e1 pmon slice #4 0280h- 02ffh t1/e1 pmon slice #5 0300h- 037fh t1/e1 pmon slice #6 0380h- 03ffh t1/e1 pmon slice #7 0400h- 047fh t1/e1 pmon slice #8 0480h- 04ffh t1/e1 pmon slice #9 0500h- 057fh t1/e1 pmon slice #10 0580h- 05ffh t1/e1 pmon slice #11 0600h- 067fh t1/e1 pmon slice #12 0680h- 06ffh t1/e1 pmon slice #13 0700h- 077fh t1/e1 pmon slice #14 0780h- 07ffh t1/e1 pmon slice #15 0800h- 087fh t1/e1 pmon slice #16 0880h- 08ffh t1/e1 pmon slice #17 0900h- 097fh t1/e1 pmon slice #18 0980h- 09ffh t1/e1 pmon slice #19 0a00h- 0a7fh t1/e1 pmon slice #20
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 107 address register 0a80h- 0affh t1/e1 pmon slice #21 0b00h- 0b7fh t1 pmon slice #22 0b00h t1 master configuration 0b01h reserved 0b02h t1 receive options 0b03h t1 ingress line interface configuration 0b04h t1 egress line interface configuration 0b05h t1 master ingress serial interface mode select 0b06h t1 master egress serial interface mode select 0b07h t1 master ingress parity and alarm enable 0b08h reserved 0b09h t1 master serial interface configuration 0b0ah reserved 0b0bh t1 interrupt source #1 0b0ch t1 interrupt source #2 0b0dh t1 diagnostics 0b0eh t1 prbs positioning 0b0fh reserved 0b10h rjat interrupt status 0b11h rjat reference clock divisor n1 control 0b12h rjat output clock divisor n2 control 0b13h rjat configuration 0b14h tjat interrupt status 0b15h tjat reference clock divisor n1 control 0b16h tjat output clock divisor n2 control 0b17h tjat configuration
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 108 address register 0b18h- 0b37h reserved 0b38h pmon interrupt enable/status 0b39h pmon framing bit error count 0b3ah pmon oof/cofa/far end block error count (lsb) 0b3bh pmon oof/cofa/far end block error count (msb) 0b3ch pmon bit error/crce count (lsb) 0b3dh pmon bit error/crce count (msb) 0b3eh pmon reserved 0b3fh pmon reserved 0b40h- 0b4fh reserved 0b50h prbs generator/checker control 0b51h prbs checker interrupt enable/status 0b52h prbs pattern select 0b53h prbs reserved 0b54h prbs error count register #1 0b55h prbs error count register #2 0b56h prbs error count register #3 0b57h prbs reserved 0b58h- 0b5fh reserved 0b60h t1 almi configuration 0b61h t1 almi interrupt enable 0b62h t1 almi interrupt status 0b63h t1 almi alarm detection status 0b64h- 0b6bh reserved 0b6ch t1 frmr configuration 0b6dh t1 frmr interrupt enable
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 109 address register 0b6eh t1 frmr interrupt status 0b6fh t1 frmr reserved 0b70h- 0b7fh reserved 0b80h- 0bffh t1 pmon slice #23 0c00h- 0c7fh t1 pmon slice #24 0c80h- 0cffh t1 pmon slice #25 0d00h- 0d7fh t1 pmon slice #26 0d80h- 0dffh t1 pmon slice #27 0e00h- 0e7fh t1 pmon slice #28 0e80h- 0fffh reserved 1000h- 10ffh ds3 framer and m13 multiplexer 1000h ds3 master reset 1001h ds3 master data source 1002h ds3 master unchannelized interface options 1003h ds3 master transmit line options 1004h ds3 master receive line options 1005h ds3 master alarm enable 1006h ds2 master alarm enable / ds3 network requirement bit 1007h reserved 1008h ds3 tran configuration 1009h ds3 tran diagnostic 100ah- 100bh ds3 tran reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 110 address register 100ch ds3 frmr configuration 100dh ds3 frmr interrupt enable/additional configuration 100eh ds3 frmr interrupt status 100fh ds3 frmr status 1010h ds3 pmon performance meters 1011h ds3 pmon interrupt enable/status 1012h ds3 pmon reserved 1013h ds3 pmon reserved 1014h ds3 pmon line code violation event count lsb 1015h ds3 pmon line code violation event count msb 1016h ds3 pmon framing bit error event count lsb 1017h ds3 pmon framing bit error event count msb 1018h ds3 pmon excessive zeros lsb 1019h ds3 pmon excessive zeros msb 101ah ds3 pmon parity error event count lsb 101bh ds3 pmon parity error event count msb 101ch ds3 pmon path parity error event count lsb 101dh ds3 pmon path parity error event count msb 101eh ds3 pmon febe event count lsb 101fh ds3 pmon febe event count msb 1020h ds3 tdpr configuration 1021h ds3 tdpr upper transmit threshold 1022h ds3 tdpr lower interrupt threshold 1023h ds3 tdpr interrupt enable 1024h ds3 tdpr interr upt status/udr clear 1025h ds3 tdpr transmit data 1026h- 1027h ds3 tdpr reserved 1028h ds3 rdlc configuration
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 111 address register 1029h ds3 rdlc interrupt control 102ah ds3 rdlc status 102bh ds3 rdlc data 102ch ds3 rdlc primary address match 102dh ds3 rdlc secondary address match 102eh- 102fh ds3 rdlc reserved 1030h prgd control 1031h prgd interrupt enable/status 1032h prgd length 1033h prgd tap 1034h prgd error insertion 1035h- 1037h prgd reserved 1038h prgd pattern insertion register #1 1039h prgd pattern insertion register #2 103ah prgd pattern insertion register #3 103bh prgd pattern insertion register #4 103ch prgd pattern detector register #1 103dh prgd pattern detector register #2 103eh prgd pattern detector register #3 103fh prgd pattern detector register #4 1040h mx23 configuration 1041h mx23 demux ais insert 1042h mx23 mux ais insert 1043h mx23 loopback activate 1044h mx23 loopback request insert 1045h mx23 loopback request detect 1046h mx23 loopback request interrupt
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 112 address register 1047h mx23 reserved 1048h feac xboc control 1049h feac xboc code 104ah feac rboc configuration/interrupt enable 104bh feac rboc interrupt status 104ch- 105fh reserved 1060h ds2 frmr #1 configuration 1061h ds2 frmr #1 interrupt enable 1062h ds2 frmr #1 interrupt status 1063h ds2 frmr #1 status 1064h ds2 frmr #1 monitor interrupt enable/status 1065h ds2 frmr #1 ferr count 1066h ds2 frmr #1 perr count (lsb) 1067h ds2 frmr #1 perr count (msb) 1068h- 106fh reserved 1070h mx12 #1 configuration and control 1071h mx12 #1 loopback code select 1072h mx12 #1 mux/demux ais insert 1073h mx12 #1 loopback activate 1074h mx12 #1 loopback interrupt 1075h- 1077h mx12 #1 reserved 1078h- 107fh reserved 1080h- 1087h ds2 frmr #2 registers 1088h- 108fh reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 113 address register 1090h- 1097h mx12 #2 registers 1098h- 109fh reserved 10a0h- 10a7h ds2 frmr #3 registers 10a8h- 10afh reserved 10b0h- 10b7h mx12 #3 registers 10b8h- 10bfh reserved 10c0h- 10c7h ds2 frmr #4 registers 10c8h- 10cfh reserved 10d0h- 10d7h mx12 #4 registers 10d8h- 10dfh reserved 10e0h- 10e7h ds2 frmr #5 registers 10e8h- 10efh reserved 10f0h- 10f7h mx12 #5 registers 10f8h- 10ffh reserved 1100h- 1107h ds2 frmr #6 registers 1108h- 110fh reserved 1110h- 1117h mx12 #6 registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 114 address register 1118h- 111fh reserved 1120h- 1127h ds2 frmr #7 registers 1128h- 112fh reserved 1130h- 1137h mx12 #7 registers 1138h- 11ffh reserved 1200h- 16ffh sonet/sdh mappe r and demapper 1200h sonet/sdh master configuration 1201h sonet/sdh master ingress configuration 1202h sonet/sdh master egress configuration 1203h sonet/sdh master ingress vtpp configuration 1204h sonet/sdh master egress vtpp configuration 1205h sonet/sdh master rtop configuration 1206h sonet/sdh master tributary alarm ais control 1207h sonet/sdh master tributary remote defect indication control 1208h sonet/sdh master tributar y auxiliary remote defect indication control 1209h sonet/sdh master ds3 clock generation control 120ah sonet/sdh master loopback control 120bh sonet/sdh telecom bus signal monitor, accumulation trigger 120ch- 121fh sonet/sdh reserved 1220h- 123fh ingress piso reserved 1240h vtpp ingress, tu #1 in tug2 #1, configuration and status
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 115 address register 1241h vtpp ingress, tu #1 in tug2 #1, alarm status 1242h vtpp ingress, tu #1 in tug2 #2, configuration and status 1243h vtpp ingress, tu #1 in tug2 #2, alarm status 1244h vtpp ingress, tu #1 in tug2 #3, configuration and status 1245h vtpp ingress, tu #1 in tug2 #3, alarm status 1246h vtpp ingress, tu #1 in tug2 #4, configuration and status 1247h vtpp ingress, tu #1 in tug2 #4, alarm status 1248h vtpp ingress, tu #1 in tug2 #5, configuration and status 1249h vtpp ingress, tu #1 in tug2 #5, alarm status 124ah vtpp ingress, tu #1 in tug2 #6, configuration and status 124bh vtpp ingress, tu #1 in tug2 #6, alarm status 124ch vtpp ingress, tu #1 in tug2 #7, configuration and status 124dh vtpp ingress, tu #1 in tug2 #7, alarm status 124eh vtpp ingress, tu #1 in tug2 #1 to tug2 #7, lop interrupt 124fh vtpp ingress, tu #1 in tug2 #1 to tug2 #7, ais interrupt 1250h- 125dh vtpp ingress, tu #2 in tug2 #1 to tug2 #7, configuration and status/alarm status 125eh vtpp ingress, tu #2 in tug2 #1 to tug2 #7, lop interrupt 125fh vtpp ingress, tu #2 in tug2 #1 to tug2 #7 ais interrupt 1260h- 126dh vtpp ingress, tu #3 in tug2 #1 to tug2 #7, configuration and status/alarm status 126eh vtpp ingress, tu #3 in tug2 #1 to tug2 #7, lop interrupt 126fh vtpp ingress, tu #3 in tug2 #1 to tug2 #7, ais interrupt 1270h- 127dh vtpp ingress, tu #4 in tug2 #1 to tug2 #7, configuration and status/alarm status 127eh vtpp ingress, tu #4 in tug2 #1 to tug2 #7, lop interrupt 127fh vtpp ingress, tu #4 in tug2 #1 to tug2 #7, ais interrupt
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 116 address register 1280h rtdm tu #1 in tug2 #1 of tug3 #1, control 1281h rtdm tu #1 in tug2 #2 of tug3 #1, control 1282h rtdm tu #1 in tug2 #3 of tug3 #1, control 1283h rtdm tu #1 in tug2 #4 of tug3 #1, control 1284h rtdm tu #1 in tug2 #5 of tug3 #1, control 1285h rtdm tu #1 in tug2 #6 of tug3 #1, control 1286h rtdm tu #1 in tug2 #7 of tug3 #1, control 1287h rtdm reserved 1288h- 128eh rtdm tu #2 in tug2 #1 to tug#7 of tug3 #1, control 128fh rtdm reserved 1290h- 1296h rtdm tu #3 in tug2 #1 to tug#7 of tug3 #1, control 1297h rtdm reserved 1298h- 129eh rtdm tu #4 in tug2 #1 to tug#7 of tug3 #1, control 129fh rtdm reserved 12a0h- 12beh rtdm tus #1-4, in tug2s #1-7 of tug3 #2, control 12bfh rtdm reserved 12c0h- 12deh rtdm tus #1-4, in tug2s #1-7 of tug3 #3, control 12dfh rtdm reserved 12e0h rtdm pointer justification rate control 12e1h rtdm reserved 12e2h rtdm time switch page control 12e3h rtdm indirect time switch tributary ram status and control 12e4h rtdm indirect time switch internal link 12e5h rtdm indirect time switch tributary
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 117 address register 12e6h rtdm demap state vector ram address 12e7h rtdm demap state vector ram control and data 12e8h rtdm demap debug state vector ram data 12e9h rtdm demap state vector ram data 12eah rtdm demap state vector ram data 12ebh rtdm demap state vector ram data 12ech- 12ffh reserved 1300h rtop tu #1 in tug2 #1, configuration 1301h rtop tu #1 in tug2 #1, configuration and alarm status 1302h rtop tu #1 in tug2 #1, expected path signal label 1303h rtop tu #1 in tug2 #1, accepted path signal label 1304h rtop tu #1 in tug2 #1, bip-2 error count lsb 1305h rtop tu #1 in tug2 #1, bip-2 error count msb 1306h rtop tu #1 in tug2 #1, febe error count lsb 1307h rtop tu #1 in tug2 #1, febe error count msb 1308h- 130fh rtop tu #1 in tug2 #2, configuration and status registers 1310h- 1317h rtop tu #1 in tug2 #3, configuration and status registers 1318h- 131fh rtop tu #1 in tug2 #4, configuration and status registers 1320h- 1327h rtop tu #1 in tug2 #5, configuration and status registers 1328h- 132fh rtop tu #1 in tug2 #6, configuration and status registers 1330h- 1337h rtop tu #1 in tug2 #7, configuration and status registers 1338h rtop tu #1 in tug2 #1 to tug2 #7, copsl interrupt 1339h rtop tu #1 in tug2 #1 to tug2 #7, pslm interrupt 133ah rtop tu #1 in tug2 #1 to tug2 #7, pslu interrupt
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 118 address register 133bh rtop tu #1 in tug2 #1 to tug2 #7, rdi interrupt 133ch rtop tu #1 in tug2 #1 to tug2 #7, rfi interrupt 133dh rtop tu #1 in tug2 #1 to tug2 #7, inband error reporting configuration 133eh- 133fh rtop reserved 1340h- 1347h rtop tu #2 in tug2 #1, configuration and status registers 1348h- 134fh rtop tu #2 in tug2 #2, configuration and status registers 1350h- 1357h rtop tu #2 in tug2 #3, configuration and status registers 1358h- 135fh rtop tu #2 in tug2 #4, configuration and status registers 1360h- 1367h rtop tu #2 in tug2 #5, configuration and status registers 1368h- 136fh rtop tu #2 in tug2 #6, configuration and status registers 1370h- 1377h rtop tu #2 in tug2 #7, configuration and status registers 1378h rtop tu #2 in tug2 #1 to tug2 #7, copsl interrupt 1379h rtop tu #2 in tug2 #1 to tug2 #7, pslm interrupt 137ah rtop tu #2 in tug2 #1 to tug2 #7, pslu interrupt 137bh rtop tu #2 in tug2 #1 to tug2 #7, rdi interrupt 137ch rtop tu #2 in tug2 #1 to tug2 #7, rfi interrupt 137dh rtop tu #2 in tug2 #1 to tug2 #7, inband error reporting configuration 137eh- 137fh rtop reserved 1380h- 1387h rtop tu #3 in tug2 #1, configuration and status registers 1388h- 138fh rtop tu #3 in tug2 #2, configuration and status registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 119 address register 1390h- 1397h rtop tu #3 in tug2 #3, configuration and status registers 1398h- 139fh rtop tu #3 in tug2 #4, configuration and status registers 13a0h- 13a7h rtop tu #3 in tug2 #5, configuration and status registers 13a8h- 13afh rtop tu #3 in tug2 #6, configuration and status registers 13b0h- 13b7h rtop tu #3 in tug2 #7, configuration and status registers 13b8h rtop tu #3 in tug2 #1 to tug2 #7, copsl interrupt 13b9h rtop tu #3 in tug2 #1 to tug2 #7, pslm interrupt 13bah rtop tu #3 in tug2 #1 to tug2 #7, pslu interrupt 13bbh rtop tu #3 in tug2 #1 to tug2 #7, rdi interrupt 13bch rtop tu #3 in tug2 #1 to tug2 #7, rfi interrupt 13bdh rtop tu #3 in tug2 #1 to tug2 #7, inband error reporting configuration 13beh- 13bfh rtop reserved 13c0h- 13c7h rtop tu #4 in tug2 #1, configuration and status registers 13c8h- 13cfh rtop tu #4 in tug2 #2, configuration and status registers 13d0h- 13d7h rtop tu #4 in tug2 #3, configuration and status registers 13d8h- 13dfh rtop tu #4 in tug2 #4, configuration and status registers 13e0h- 13e7h rtop tu #4 in tug2 #5, configuration and status registers 13e8h- 13efh rtop tu #4 in tug2 #6, configuration and status registers 13f0h- 13f7h rtop tu #4 in tug2 #7, configuration and status registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 120 address register 13f8h rtop tu #4 in tug2 #1 to tug2 #7, copsl interrupt 13f9h rtop tu #4 in tug2 #1 to tug2 #7, pslm interrupt 13fah rtop tu #4 in tug2 #1 to tug2 #7, pslu interrupt 13fbh rtop tu #4 in tug2 #1 to tug2 #7, rdi interrupt 13fch rtop tu #4 in tug2 #1 to tug2 #7, rfi interrupt 13fdh rtop tu #4 in tug2 #1 to tug2 #7, inband error reporting configuration 13feh- 13ffh rtop reserved 1400h vtpp egress, tu #1 in tug2 #1, configuration and status 1401h vtpp egress, tu #1 in tug2 #1, alarm status 1402h vtpp egress, tu #1 in tug2 #2, configuration and status 1403h vtpp egress, tu #1 in tug2 #2, alarm status 104h vtpp egress, tu #1 in tug2 #3, configuration and status 1405h vtpp egress, tu #1 in tug2 #3, alarm status 1406h vtpp egress, tu #1 in tug2 #4, configuration and status 1407h vtpp egress, tu #1 in tug2 #4, alarm status 1408h vtpp egress, tu #1 in tug2 #5, configuration and status 1409h vtpp egress, tu #1 in tug2 #5, alarm status 140ah vtpp egress, tu #1 in tug2 #6, configuration and status 140bh vtpp egress, tu #1 in tug2 #6, alarm status 140ch vtpp egress, tu #1 in tug2 #7, configuration and status 140dh vtpp egress, tu #1 in tug2 #7, alarm status 140eh vtpp egress, tu #1 in tug2 #1 to tug2 #7, lop interrupt 140fh vtpp egress, tu #1 in tug2 #1 to tug2 #7, ais interrupt 1410h- 141dh vtpp egress, tu #2 in tug2 #1 to tug2 #7, configuration and status/alarm status 141eh vtpp egress, tu #2 in tug2 #1 to tug2 #7, lop interrupt
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 121 address register 141fh vtpp egress, tu #2 in tug2 #1 to tug2 #7 ais interrupt 1420h- 142dh vtpp egress, tu #3 in tug2 #1 to tug2 #7, configuration and status/alarm status 142eh vtpp egress, tu #3 in tug2 #1 to tug2 #7, lop interrupt 142fh vtpp egress, tu #3 in tug2 #1 to tug2 #7, ais interrupt 1430h- 143dh vtpp egress, tu #4 in tug2 #1 to tug2 #7, configuration and status/alarm status 143eh vtpp egress, tu #4 in tug2 #1 to tug2 #7, lop interrupt 143fh vtpp egress, tu #4 in tug2 #1 to tug2 #7, ais interrupt 1440h- 147fh reserved 1480h trap tu #1 in tug2 #1 of tu3 #1, control 1481h trap tu #1 in tug2 #2 of tu3 #1, control 1482h trap tu #1 in tug2 #3 of tu3 #1, control 1483h trap tu #1 in tug2 #4 of tu3 #1, control 1484h trap tu #1 in tug2 #5 of tu3 #1, control 1485h trap tu #1 in tug2 #6 of tu3 #1, control 1486h trap tu #1 in tug2 #7 of tu3 #1, control 1487h trap tu #1 in tug2 #1 to tug2 #7 of tug3 #1, egress ais control 1488h- 148eh trap tu #2 in tug2 #1 to tug#7 of tu3 #1, control 148fh trap tu#2 in tug2 #1 to tug2 #7 of tu3 #1, egress ais control 1490h- 1496h trap tu #3 in tug2 #1 to tug#7 of tu3 #1, control 1497h trap tu#3 in tug2 #1 to tug2 #7 of tu3 #1, egress ais control 1498h- 149eh trap tu #4 in tug2 #1 to tug#7 of tu3 #1, control
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 122 address register 149fh trap tu#4 in tug2 #1 to tug2 #7 of tu3 #1, egress ais control 14a0h- 14bfh trap tus #1 to 4 in tug2s #1 to 7 of tug3 #2, control and egress ais control 14c0h- 14dfh trap tus #1 to 4 in tug2s #1 to 7 of tug3 #3, control and egress ais control 14e0h trap indirect remote alarm page address 14e 1h trap indirect remote alarm tributary address 14e2h trap indirect datapath tributary data 14e3h trap rdi control 14e4h- 14e7h trap reserved 14e8h trap remote parallel alarm port tug2 #1 of tug3 #1 configuration 14e9h- 14eeh trap remote parallel alarm port tug2 #2 to tug2 #7 of tug3 #1 configuration 14efh trap reserved 14f0h- 14f6h trap remote parallel alarm port tug2 #1 to tug2 #7 of tug3 #2 configuration 14f7h trap reserved 14f8h- 14feh trap remote parallel alarm port tug2 #1 to tug2 #7 of tug3 #3 configuration 14ffh trap reserved 1500h ttop tu #1 in tug2 #1 of tug3 #1, control 1501h ttop tu #1 in tug2 #2 of tug3 #1, control 1502h ttop tu #1 in tug2 #3 of tug3 #1, control 1503h ttop tu #1 in tug2 #4 of tug3 #1, control 1504h ttop tu #1 in tug2 #5 of tug3 #1, control 1505h ttop tu #1 in tug2 #6 of tug3 #1, control 1506h ttop tu #1 in tug2 #7 of tug3 #1, control
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 123 address register 1507h ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #1bip diagnostic control 1508h- 150eh ttop tu #2 in tug2 #1 to tug#7 of tug3 #1, control 150fh ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #,1bip diagnostic control 1510h- 1516h ttop tu #3 in tug2 #1 to tug#7 of tug3 #1, control 1517h ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #1,bip diagnostic control 1518h- 151eh ttop tu #4 in tug2 #1 to tug#7 of tug3 #1, control 151fh ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #1, bip diagnostic control 1520h- 153fh ttop tus #1 to 4 in tug2s #1 to 7 of tug3 #2, control and bip diagnostic control 1540h- 155fh ttop tus #1 to 4 in tug2s #1 to 7 of tug3 #3, control and bip diagnostic control 1560h ttop tug3 #1control 1561h ttop tug3 #2control 1562h ttop tug3 #3control 1563h reserved 1564h ttop trail trace identifier page select 1565h ttop indirect trail trace identifier tributary select 1566h ttop indirect trail trace identifier buffer address 1567h ttop indirect trail trace identifier buffer data 1568h- 157fh reserved 1580h ttmp tu #1 in tug2 #1 of tug3 #1, tributary control 1581h ttmp tu #1 in tug2 #2 of tug3 #1, tributary control 1582h ttmp tu #1 in tug2 #3 of tug3 #1, tributary control 1583h ttmp tu #1 in tug2 #4 of tug3 #1, tributary control
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 124 address register 1584h ttmp tu #1 in tug2 #5 of tug3 #1, tributary control 1585h ttmp tu #1 in tug2 #6 of tug3 #1, tributary control 1586h ttmp tu #1 in tug2 #7 of tug3 #1, tributary control 1587h reserved 1588h- 158eh ttmp tu #2 in tug2 #1 to tug#7 of tug3 #1, tributary control 158fh reserved 1590h- 1596h ttmp tu #3 in tug2 #1 to tug#7 of tug3 #1, tributary control 1597h reserved 1598h- 159eh ttmp tu #4 in tug2 #1 to tug#7 of tug3 #1, tributary control 159fh reserved 15a0h- 15bfh ttmp tus #1 to 4 in tug2s #1 to 7 of tug3 #2, tributary control 15c0h- 15dfh ttmp tus #1 to 4 in tug2s #1 to 7 of tug3 #3, tributary control 15e0h ttmp reserved 15e1h ttmp time switch page control 15e2h ttmp indirect time switch ram control and status 15e3h ttmp indirect time switch tributary address 15e4h ttmp indirect time switch tributary data 15e5h ttmp telecom interface configuration 15e6h ttmp fifo depth 15e7h ttmp map svram capture address 15e8h ttmp map svram control signals and bistinit abort 15e9h- 15f5h ttmp map svram data 15f6h- 15ffh reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 125 address register 1600h- 163fh egress sipo reserved 1640h d3md control 1641h d3md interrupt status 1642h d3md interrupt enable 1643h reserved 1644h d3ma control 1645h d3ma interrupt status 1646h d3ma interrupt enable 1647h reserved 1648h- 16ffh reserved 1700h- 179fh sbi interface 1700h sbi master reset / bus signal monitor 1701h sbi master configuration 1702h sbi bus master configuration 1703h- 170fh sbi reserved 1710h exsbi control 1711h exsbi fifo underrun interrupt status 1712h exsbi fifo overrun interrupt status 1713h exsbi tributary ram indirect access address 1714h exsbi tributary ram indirect access control 1715h exsbi reserved 1716h exsbi tributary control indirect access data 1717h exsbi sbi parity error interrupt status 161ah exsbi reserved 161bh exsbi reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 126 address register 1718h- 171dh exsbi reserved 171eh exsbi depth check interrupt status 171fh exsbi extract external resynch interrupt status 1720h insbi control 1721h insbi fifo underrun interrupt status 1722h insbi fifo overrun interrupt status 1723h insbi tributary register indirect access address 1724h insbi tributary register indirect access control 1725h insbi reserved 1726h insbi tributary control indirect access data 1609h- 160eh insbi reserved 1727h- 172fh insbi reserved 1731h insbi depth check interrupt status 1732h insbi insert external resynch interrupt status 1733h- 173fh insbi reserved 1740h- 175fh sbi sipo reserved 1780h- 179fh sbi piso reserved 1780h- 1fffh reserved for all register accesse s, csb must be low.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 127 10 normal mode register description normal mode registers are used to configure and monitor the operation of the temap. normal mode registers (as opposed to test mode registers) are selected when trs (a[13]) is low. notes on normal mode register bits: 1) writing values into unused register bits typically has no effect. however, to ensure software compatibility with futu re, feature-enhanced ve rsions of the product, unused register bit must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2) all configuration bits that can be written into can also be read back. this allows the processor controlling the temap to determine the programming state of the block. 3) writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4) writing into read-only normal mode register bit locations does not affect temap operation unless otherwise noted. the register descriptions are contained in a separate temap register description document.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 128 11 test features description the temap contains test features for both production testing and board testing. simultaneously asserting the csb, rdb and wrb inputs causes all output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the temap. test mode registers (as opposed to normal mode registers) are selected when trs (a[13]) is high. test mode register memory map address register 0000h- 1fffh normal mode registers 2000h master test register 2080h- 20ffh t1/e1 pmon #1 2090h- 2093h rjat test registers 2094h- 2097h tjat test registers 2098h- 20b7h reserved 20b8h- 20bfh pmon test registers 20c0h- 20cfh reserved 20d0h- 20d7h prbs test registers 20d8h- 20dfh reserved 20e0h- 20e3h t1 almi test registers (t1 mode)
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 129 20e4h- 20ebh reserved (t1 mode) 20ech- 20efh t1 frmr test registers (t1 mode) 20e0h- 20efh e1 frmr test registers (e1 mode) 20f0h- 20ffh reserved 2100h- 217fh t1/e1 pmon #2 2180h- 21ffh t1/e1 pmon #3 2200h- 227fh t1/e1 pmon #4 2280h- 22ffh t1/e1 pmon #5 2300h- 237fh t1/e1 pmon #6 2380h- 23ffh t1/e1 pmon #7 2400h- 247fh t1/e1 pmon #8 2480h- 24ffh t1/e1 pmon #9 2500h- 257fh t1/e1 pmon #10 2580h- 25ffh t1/e1 pmon #11 2600h- 267fh t1/e1 pmon #12 2680h- 26ffh t1/e1 pmon #13 2700h- 277fh t1/e1 pmon #14
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 130 2780h- 27ffh t1/e1 pmon #15 2800h- 287fh t1/e1 pmon #16 2880h- 28ffh t1/e1 pmon #17 2900h- 297fh t1/e1 pmon #18 2980h- 29ffh t1/e1 pmon #19 2a00h- 2a7fh t1/e1 pmon #20 2a80h- 2affh t1/e1 pmon #21 2b00h- 2b7fh t1 pmon #22 2b80h- 2bffh t1 pmon #23 2c00h- 2c7fh t1 pmon #24 2c80h- 2cffh t1 pmon #25 2d00h- 2d7fh t1 pmon #26 2d80h- 2dffh t1 pmon #27 2e00h- 2e7fh t1 pmon #28 2e80h- 2fffh reserved 3000h- 30ffh ds3 framer and m13 multiplexer 3000h- 3007h reserved
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 131 3008h- 300bh ds3 tran test registers 300ch- 300fh ds3 frmr test registers 3010h- 301fh ds3 pmon test registers 3020h- 3027h ds3 tdpr test registers 3028h- 3029h ds3 rdlc test registers 3030h- 303fh prgd test registers 3040h- 3047h mx23 test registers 3048h- 304bh feac xboc test registers 304ch- 305fh reserved 3060h- 3067h ds2 frmr #1 test registers 3068h- 306fh reserved 3070h- 3077h mx12 #1 test registers 3078h- 307fh reserved 3080h- 3087h ds2 frmr #2 test registers 3088h- 308fh reserved 3090h- 3097h mx12 #2 test registers 3098h- 309fh reserved 30a0h- 30a7h ds2 frmr #3 test registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 132 30a8h- 30afh reserved 30b0h- 30b7h mx12 #3 test registers 30b8h- 30bfh reserved 30c0h- 30c7h ds2 frmr #4 test registers 30c8h- 30cfh reserved 30d0h- 30d7h mx12 #4 test registers 30d8h- 30dfh reserved 30e0h- 30e7h ds2 frmr #5 test registers 30e8h- 30efh reserved 30f0h- 30f7h mx12 #5 test registers 30f8h- 30ffh reserved 3100h- 3107h ds2 frmr #6 test registers 3108h- 310fh reserved 3110h- 3117h mx12 #6 test registers 3118h- 311fh reserved 3120h- 3127h ds2 frmr #7 test registers 3128h- 312fh reserved 3130h- 3137h mx12 #7 test registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 133 3138h- 31ffh reserved 3200h- 36ffh sonet/sdh mappe r and demapper 3200h- 321f reserved 3220h- 323fh piso test registers 3240h- 327fh ingress vtpp test registers 3280h- 32ffh rtdm test registers 3300h- 33ffh rtop test registers 3400h- 347fh egress vtpp test registers 3480h- 34ffh trap test registers 3500h- 357fh ttop test registers 3580h- 35ffh ttmp test registers 3600h- 363fh sipo test registers 3640h- 3643h d3md test registers 3644h- 3647h d3ma test registers 3648h- 36ffh reserved 3700h- 379fh sbi interface 3700h- 370fh reserved 3710h- 371fh exsbi test registers
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 134 3720h- 373fh insbi test registers 3740h- 375fh sbi sipo test registers 3780h- 379fh sbi piso test registers 3780h- 3fffh reserved notes on register bits: 1) writing values into unused register bits has no effect. reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. 2) writeable register bits are not initialized upon reset unless otherwise noted.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 135 register 2000h: master test register bit type func tion default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 w pmctst x bit 3 w dbctrl x bit 2 r/w iotst x bit 1 w hizdata x bit 0 r/w hizio x this register is used to select temap test features. all bits, except for pmctst, are reset to zero by a hardware reset of the temap; a software reset of the temap does not affect the state of the bits in this register. pmctst: the pmctst bit is used to configure the temap for pmc's manufacturing tests. when pmctst is set to logic 1, the temap microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and can only be cleared by setting csb to logic 1. dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin while iotst is a logic 1. when the dbctrl bit is set to logic 1, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the temap to drive the data bus and holding the csb pin low tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. when iotst and pmctst are both logic 0, the dbctrl bit is ignored. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the temap for board level testing. when iotst is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 136 manipulate the outputs of the block and consequently the device outputs (refer to the "test mode 0 details" in the "test features" section). hizio: the hizio bit controls the tri-state modes of the output pins of the temap. while the hizio bit is a logic 1, all output pins of the temap, except the data bus, are held in a high-im pedance state. the microprocessor interface is still active. hizdata: the hizdata bit controls the tri-state modes of the temap. while the hizio bit is a logic 1, all output pins of the temap, except the data bus, are held in a high- impedance state. while the hizdata bit is a logic 1, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. 11.1 jtag test port the temap jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. table 11 - instruction register length - 3 bits instructions selected register instruction code ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 137 table 12 - identification register length 32 bits version number 5h part number 5365h manufacturer's identification code 0cdh device identification 553650cdh 11.1.1 boundary scan register the boundary scan register is made up of 286 boundary scan cells, divided into inout observation (in_cell), output (out_cell) and bidirectional (io_cell) cells. these cells are detailed in the following pages. the first 32 cells form the id code register and carry the code 083150cdh. the cells are arranged as follows: table 13 - boundary scan chain pin/enable register bit cell type device i.d. hiz 0 out_cell - iclk[28] 1 out_cell - iclk[27] 2 out_cell - iclk[20] 3 out_cell - iclk[19] 4 out_cell - unconnected 5 out_cell - eclk[28]_oen 6 out_cell - eclk[28] 7 io_cell - eclk[27]_oen 8 out_cell - eclk[27] 9 io_cell - eclk[20]_oen 10 out_cell - eclk[20] 11 io_cell - eclk[19]_oen 12 out_cell - eclk[19] 13 io_cell - eclk[12]_oen 14 out_cell - eclk[12] 15 io_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 138 pin/enable register bit cell type device i.d. eclk[11]_oen 16 out_cell - eclk[11] 17 io_cell - unconnected 18 out_cell - unconnected 19 out_cell - iclk[12] 20 out_cell - iclk[11] 21 out_cell - id[12] 22 out_cell - id[11] 23 out_cell - id[26] 24 out_cell - id[25] 25 out_cell - iclk[26] 26 out_cell - iclk[25] 27 out_cell - unconnected 28 out_cell - unconnected 29 out_cell - eclk[26]_oen 30 out_cell - eclk[26] 31 io_cell - eclk[25]_oen 32 out_cell - eclk[25] 33 io_cell - ed[26] 34 in_cell - ed[25] 35 in_cell - ed[18] 36 in_cell - ctclk 37 in_cell - logic 0 38 in_cell - logic 0 39 in_cell - logic 0 40 in_cell - logic 0 41 in_cell - logic 0 42 in_cell - ed[17] 43 in_cell - clk52m 44 in_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 139 pin/enable register bit cell type device i.d. ed[10] 45 in_cell - unconnected 46 out_cell - eclk[18]_oen 47 out_cell - eclk[18] 48 io_cell - eclk[17]_oen 49 out_cell - eclk[17] 50 io_cell - eclk[10]_oen 51 out_cell - eclk[10] 52 io_cell - ed[9] 53 in_cell - iclk[18] 54 out_cell - iclk[17] 55 out_cell - id[18] 56 out_cell - id[17] 57 out_cell - unconnected 58 out_cell - unconnected 59 out_cell - unconnected 60 out_cell - unconnected 61 out_cell - unconnected 62 out_cell - id[10] 63 out_cell - id[9] 64 out_cell - iclk[10] 65 out_cell - iclk[9] 66 out_cell - eclk[9]_oen 67 out_cell - eclk[9] 68 io_cell - eclk[2]_oen 69 out_cell - eclk[2] 70 io_cell - iclk[2] 71 out_cell - ed[2]_ tfpi_tmfpi 72 in_cell - eclk[1]_tgapclk_oen 73 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 140 pin/enable register bit cell type device i.d. eclk[1]_tgapclk 74 io_cell - ed[1]_ tdati 75 in_cell - id[1]_ rdato 76 out_cell - id[2]_ rovrhd 77 out_cell - iclk[1]_rsclk 78 out_cell - rfpo_rmfpo 79 out_cell - ticlk 80 in_cell - rclk 81 in_cell - rpos_rdat 82 in_cell - rneg_rlcv 83 in_cell - tclk 84 out_cell - tpos_tdat 85 out_cell - tneg_tmfp 86 out_cell - ladata[0]_oen 87 out_cell - ladata[0] 88 out_cell - ladata[1]_oen 89 out_cell - ladata[1] 90 out_cell - ladata[2]_oen 91 out_cell - ladata[2] 92 out_cell - ladata[3]_oen 93 out_cell - ladata[3] 94 out_cell - ladata[4]_oen 95 out_cell - ladata[4] 96 out_cell - ladata[5]_oen 97 out_cell - ladata[5] 98 out_cell - ladata[6]_oen 99 out_cell - ladata[6] 100 out_cell - ladata[7]_oen 101 out_cell - ladata[7] 102 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 141 pin/enable register bit cell type device i.d. ladp_oen 103 out_cell - ladp 104 out_cell - lapl_oen 105 out_cell - lapl 106 out_cell - lac1j1v1 107 out_cell - laoe 108 out_cell - lrefclk 109 in_cell - ldais 110 in_cell - lac1 111 in_cell - ldtpl 112 in_cell - lddata[0] 113 in_cell - lddata[1] 114 in_cell - lddata[2] 115 in_cell - lddata[3] 116 in_cell - lddata[4] 117 in_cell - lddata[5] 118 in_cell - lddata[6] 119 in_cell - lddata[7] 120 in_cell - lddp 121 in_cell - ldpl 122 in_cell - ldv5 123 in_cell - ldc1j1v1 124 in_cell - radeast 125 in_cell - radeastclk 126 in_cell - radeastfp 127 in_cell - radwest 128 in_cell - radwestclk 129 in_cell - radwestfp 130 in_cell - iclk[3] 131 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 142 pin/enable register bit cell type device i.d. iclk[4] 132 out_cell - id[3] 133 out_cell - eclk[3]_oen 134 out_cell - eclk[3] 135 io_cell - eclk[4]_oen 136 out_cell - eclk[4] 137 io_cell - eclk[5]_oen 138 out_cell - eclk[5] 139 io_cell - unconnected 140 out_cell - unconnected 141 out_cell - unconnected 142 out_cell - unconnected 143 out_cell - unconnected 144 out_cell - unconnected 145 out_cell - iclk[5] 146 out_cell - iclk[6] 147 out_cell - eclk[6]_oen 148 out_cell - eclk[6] 149 io_cell - eclk[13]_oen 150 out_cell - eclk[13] 151 io_cell - eclk[14]_oen 152 out_cell - eclk[14] 153 io_cell - eclk[21]_oen 154 out_cell - eclk[21] 155 io_cell - eclk[22]_oen 156 out_cell - eclk[22] 157 io_cell - eclk[7]_oen 158 out_cell - eclk[7] 159 io_cell - eclk[8]_oen 160 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 143 pin/enable register bit cell type device i.d. eclk[8] 161 io_cell - unconnected 162 out_cell - unconnected 163 out_cell - id[4] 164 out_cell - id[5] 165 out_cell - id[6] 166 out_cell - id[13] 167 out_cell - id[14] 168 out_cell - ed[3] 169 in_cell - ed[4] 170 in_cell - ed[5] 171 in_cell - ed[6] 172 in_cell - ed[13] 173 in_cell - ed[14] 174 in_cell - id[21] 175 out_cell - id[22] 176 out_cell - iclk[13] 177 out_cell - iclk[14] 178 out_cell - unconnected 179 out_cell - unconnected 180 out_cell - unconnected 181 out_cell - unconnected 182 out_cell - unconnected 183 out_cell - unconnected 184 out_cell - iclk[21] 185 out_cell - iclk[22] 186 out_cell - iclk[7] 187 out_cell - iclk[8] 188 out_cell - id[7] 189 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 144 pin/enable register bit cell type device i.d. id[8] 190 out_cell - iclk[15] 191 out_cell - iclk[16] 192 out_cell - iclk[23] 193 out_cell - iclk[24] 194 out_cell - ed[22] 195 in_cell - ed[21] 196 in_cell - recvclk1 197 out_cell - recvclk2 198 out_cell - xclk 199 in_cell - eclk[15]_oen 200 out_cell - eclk[15] 201 io_cell - eclk[16]_oen 202 out_cell - eclk[16] 203 io_cell - eclk[23]_oen 204 out_cell - eclk[23] 205 io_cell - eclk[24]_oen 206 out_cell - eclk[24] 207 io_cell - rstb 208 in_cell - a[13] 209 in_cell - a[12] 210 in_cell - a[11] 211 in_cell - a[10] 212 in_cell - a[9] 213 in_cell - a[8] 214 in_cell - a[7] 215 in_cell - a[6] 216 in_cell - a[5] 217 in_cell - a[4] 218 in_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 145 pin/enable register bit cell type device i.d. a[3] 219 in_cell - a[2] 220 in_cell - a[1] 221 in_cell - a[0] 222 in_cell - rdb 223 in_cell - wrb 224 in_cell - ale 225 in_cell - intb 226 out_cell - csb 227 in_cell - d[0]_oen 228 out_cell - d[0] 229 io_cell - d[1]_oen 230 out_cell - d[1] 231 io_cell - d[2]_oen 232 out_cell - d[2] 233 io_cell - d[3]_oen 234 out_cell - d[3] 235 io_cell - d[4]_oen 236 out_cell - d[4] 237 io_cell - d[5]_oen 238 out_cell - d[5] 239 io_cell - d[6]_oen 240 out_cell - d[6] 241 io_cell - d[7]_oen 242 out_cell - d[7] 243 io_cell - id[15]_sddata[0]_oen 244 out_cell - id[15]_sddata[0] 245 out_cell - id[16]_sddata[1]_oen 246 out_cell - id[16]_sddata[1] 247 out_cell -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 146 pin/enable register bit cell type device i.d. id[19]_sddata[2]_oen 248 out_cell - id[19]_sddata[2] 249 out_cell - id[20]_sddata[3]_oen 250 out_cell - id[20]_sddata[3] 251 out_cell - id[23]_sddata[4]_oen 252 out_cell - id[23]_sddata[4] 253 out_cell - id[24]_sddata[5]_oen 254 out_cell 1 id[24]_sddata[5] 255 out_cell 0 id[27]_sddata[6]_oen 256 out_cell 1 id[27]_sddata[6] 257 out_cell 1 id[28]_sddata[7]_oen 258 out_cell 0 id[28]_sddata[7] 259 out_cell 0 sddp_oen 260 out_cell 1 sddp 261 out_cell 1 sdv5_oen 262 out_cell 0 sdv5 263 out_cell 0 sdpl_oen 264 out_cell 0 sdpl 265 out_cell 0 sajust_req_oen 266 out_cell 1 sajust_req 267 out_cell 0 sbiact_oeb 268 out_cell 1 sbiact 269 out_cell 0 sbidet[0] 270 in_cell 0 ed[7]_sbidet[1] 271 in_cell 1 srefclk 272 in_cell 1 sc1fp_oen 273 out_cell 0 sc1fp 274 io_cell 1 ed[15]_sadata[0] 275 in_cell 1 ed[16]_sadata[1] 276 in_cell 0
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 147 pin/enable register bit cell type device i.d. ed[19]_sadata[2] 277 in_cell 0 ed[20]_sadata[3] 278 in_cell 1 ed[23]_sadata[4] 279 in_cell 0 ed[24]_sadata[5] 280 in_cell 1 ed[27]_sadata[6] 281 in_cell 0 ed[28]_sadata[7] 282 in_cell 1 ed[8]_sadp 283 in_cell 0 ed[12]_sapl 284 in_cell 1 ed[11]_sav5 285 in_cell 0 tdo tap output - tdi tap input - tck tap clock - tms tap input - trstb tap input - notes: 1. register bit 285 is the first bit of the scan chain (closest to tdi). 2. enable cell pinname_oen, tristates pin pinname when set high. 3. enable cell hiz, tristates all pins that do not have an individual pinname_oen enable signal.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 148 12 operation 12.1 ds3 frame format the temap provides support for both the c-bit parity and m23 ds3 framing formats. the ds3 frame format is shown in figure 13. figure 17: ds3 frame structure x x : x-bit channel transmit : the temap inserts the ferf signal on the x-bits. ferf generation is controlled by either the ferf bit of the ds3 tran configuration register or by detection of oof, red, los and ais, as configured by the temap master ds3 alarm enable register. receive: the temap monitors the state and detects changes in the state of the ferf signal on the x-bits. p x : p-bit channel transmit : the temap calculates the parity for the payload data over the previous m-frame and inserts it into the p1 and p2 bit positions. receive : the temap calculates the parity for the received payload. errors are accumulated in the ds3 pmon parity error event count registers. m x : m-frame alignment signal transmit : the temap generates the m-frame alignment signal (m1 = 0, m2 = 1, m3 = 0). receive : the temap finds m-frame alignment by searching for the f-bits and the m-bits. out-of-frame is removed if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f-bits.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 149 m-bit errors are counted in the ds3 pmon framing bit error event count registers. when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames, an out-of-frame defect is asserted (if mbdis in the ds3 framer configuration register is a logic 0). f x : m-subframe alignment signal transmit : the temap generates the m-subframe alignment signal (f1=1, f2=0, f3=0, f4=1). receive : the temap finds m-frame alignment by searching for the f-bits and the m-bits. out-of-frame is removed if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f-bits. f-bit errors are counted in the ds3 pmon framing bit error event count registers. an out-of frame defect is asserted if 3 f-bit errors out of 8 or 16 consecutive f-bits are observed (as selected by the m3o8 bit in the ds3 frmr configuration register). c x : c-bit channels transmit : when configured for m23 applications, the c-bits are forced to logic 1 with the exception of the c-bit parity id bit (the first c-bit of the first m-subframe), which is forced to toggle every m-frame. when configured for c-bit parity applications, the c-bit parity id bit is forced to logic 1. the second c-bit in m-subframe 1 is set to logic 1. the third c-bit in m-subframe 1 provides a far-end alarm and control (feac) signal. the feac channel is sourced by the ds3 xboc block. the 3 c- bits in m-subframe 3 carry path parity information. the value of these 3 c- bits is the same as that of the p-bits. the 3 c-bits in m-subframe 4 are the febe bits. febe transmission is controlled by the dfebe bit in the ds3 tran diagnostic register and by the detection of receive framing bit and path parity errors. the 3 c-bits in m-subframe 5 contain the 28.2 kbit/s path maintenance datalink. these bits are inserted from the ds3 tdpr hdlc controller. the c-bits in m-subframes 2, 6, and 7 are unused and are set to logic 1. receive : the cbitv register bit in the ds3 frmr status register is used to report the state of the c-bit parity id bit, and hence whether a m23 or c- bit parity ds3 signal stream is being received. the feac channel on the third c-bit in m-subframe 1 is detected by the ds3 rboc block. path parity errors and detected febes on the c-bits in m-subframes 3 and 4 are reported in the ds3 pmon path parity error event count and febe event count registers respectively. the path maintenance datalink signal is extracted by theds3 rdlc hdlc receiver (if enabled).
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 150 12.2 servicing interrupts the temap will assert intb to logic 0 when a condition which is configured to produce an interrupt occurs. to find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. read the bits of the temap master interrupt source register (0020h) to identify which of the eight interrupt registers (0021h-0028h) needs to be read to identify the interrupt. for example, a logic one read in the ds3int register bit indicates that an interrupt identified in the master interrupt source ds3 register produced the interrupt. 2. read the bits of the second level master interrupt source register to identify the interrupt source. 3. service the interrupt. 4. if the intb pin is still logic 0, then there are still interrupts to be serviced. otherwise, all interrupts have been serviced. wait for the next assertion of intb 12.3 using the performance monitoring features the pmon blocks ar e provided for performance mo nitoring purposes. the ds3 pmon block is used to monitor ds3 per formance primitives. the pmon blocks within each t1/e1 framer slice are used to monitor t1 or e1 performance primitives. the counters in the ds3 pmon block has been sized as not to saturate if polled every second. the t1/e1 pmon event counters are of sufficient length so that the probability of counter saturati on over a one second interval is very small (less than 0.001%). an accumulation interval is initiated by writing to one of the pmon event counter register addresses or by writing to the master revision/global pmon update register. after initiating an accumulation interval, 3.5 recovered clock periods (rclk for the ds3 pmon) must be allowed to elapse to permit the pmon counter values to be properly transferred before the pmon registers may be read. the odds of any one of the t1/e1 counters saturating during a one second sampling interval go up as the bit error rate (ber) increases. at some point, the probability of counter satu ration reaches 50%. this point varies, depending upon the framing format and the type of event being counted. the ber at which the probability of counter sa turation reaches 50% is s hown for various counters in table 14 for e1 mode, and in table 15 for t1 mode.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 151 table 14 - pmon counter saturation limits (e1 mode) counter ber fer 4.0 x 10 -3 crce cannot saturate febe cannot saturate table 15 - pmon counter saturation limits (t1 mode) counter format ber fer sf 1.6 x 10 -3 esf 6.4 x 10 -2 crce sf 1.28 x 10 -1 esf cannot saturate below these 50% points, the relationship between the ber and the counter event count (averaged over many one second samples) is essentially linear. above the 50% point, the relationship between ber and the average counter event count is highly non-linear due to the likelihood of counter saturation. the following figures show this relationship for various counters and framing formats. these graphs can be used to determine the ber, given the average event count. in general, if the ber is above 10 -3 , the average counter event count cannot be used to determine the ber without considering the statistical effect of occasional counter saturation. figure 18 illustrates the expected count valu es for a range of bit error ratios in e1 mode.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 152 figure 18 - fer count vs. ber (e1 mode) since the maximum number of crc sub-multiframes that can occur in one second is 1000, the 10-bit febe and crce counters cannot saturate in one second. despite this, there is not a linear relationship between ber and crc-4 block errors due to the nature of the crc-4 calculation. at bers below 10 -4 , there tends to be no more than one bit error per sub-multiframe, so the number of crc-4 errors is generally equal to the number of bit errors, which is directly related to the ber. however, at bers above 10 -4 , each crc-4 error is often due to more than one bit error. thus , the relationship between ber and crce count becomes non-linear above a 10 -4 ber. this must be taken into account when using crc-4 counts to determine the ber. since febes ar e indications of crces at the far end, and are accumulated identically to crces, the same explanation holds for the febe event counter. the bit error rate for e1 can be ca lculated from the one-second pmon crce count by the following equation: bit error rate = 1 - 10 256 * 8 8000 8 1 log crce
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 153 figure 19 - crce count vs. ber (e1 mode) 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-03 1.00e-02 0 200 400 600 800 1000 1200 crce bit error rate figure 20 illustrates the expected count valu es for a range of bit error ratios in t1 mode. figure 20 - fer count vs. ber (t1 esf mode) 0 50 100 150 200 250 0 1 2 3 4 5 6 7 8 9 average count over many 1 second intervals b i t e r r o r r a t e ( x 1 0 ) - 2 framing bit error count per second since the maximum number of esf superfram es that can occur in one second is 333, the 9-bit bee counter cannot saturate in one second in esf framing format. despite this, there is not a linear relationship between ber and bee count, due to the nature of the crc-6 calculation. at bers below 10 -4 , there tends to be no more than one bit error per superframe, so the number of crc-6 errors is generally equal to the number of bit errors, which is directly related to the ber. however, at bers above 10 -4 , each crc-6 error is often due to more than one
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 154 bit error. thus, the relationship between ber and bee count becomes non- linear above a 10 -4 ber. this must be taken into account when using esf crc-6 counts to determine the ber. the bit error rate for t1 esf can be calculated from the one-second pmon crce count by the following equation: bit error rate = 1 - 10 193 * 24 8000 24 1 log bee figure 21 - crce count vs. ber (t1 esf mode) 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-03 1.00e-02 0 50 100 150 200 250 300 350 crce bit error rate for t1 sf format, the crce and fer count s are identical, but the fer counter is smaller and should be ignored.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 155 figure 22 - crce count vs. ber (t1 sf mode) 0 2 4 6 8 10 12 14 16 0 200 400 600 800 1000 1200 bit error event count per second b i t e r r o r r a t e ( x 1 0 ) - 2 average count over many 1 second intervals 18 20 12.4 t1/e1 framer loopback modes t1/e1 line loopback t1/e1 line loopback is initiated by setting the lloop bit to a 1 in the t1/e1 diagnostics register (000dh + n*80h, n=1 to 28). when in line loopback mode the appropriate t1/e1 streams in the temap are configured to internally connect the jitter-attenuated clock and data from the rjat to the transmit clock and data (shown as txd[x] and txclk[x] in the lineloopback diagram) going to the m13 mux and sonet/sdh mapper. the rjat may be bypassed if desired. conceptually, the data flow through a single t1/e1 performance monitor block in this loopback condition is illustrated in figure 23.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 156 figure 23: t1/e1 line loopback isif ingress interface pmon performance monitor id[1:28] iclk[1:28] rxclk[1:28] rxd[1:28] tjat digital jitter a ttenuato r esif egress interface transmitter txd[1:28] txclk[1:28] ed[1:28] ctclk* eclk[1:28] rjat digital jitter a ttenuato r tops timing options receiver li ne loopback t1/e1 diagnostic digital loopback when diagnostic digital loopback is initiated, by writing a 1 to the dloop bit in the t1/e1 diagnostics register (000dh + n*80h, n=1 to 28), the appropriate t1/e1 stream in the temap is configured to internally connect its transmit clock and data (shown as txd[x] and txclk[x] in the diagnostic loopback figure) to the receive clock and data (shown as rxd[x] and rxclk[x] in the diagnostic loopback figure) the data flow through a single t1/e1 performance monitoring block in this loopback condition is illustrated in figure 24.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 157 figure 24: t1/e1 diagnostic digital loopback isif ingress interface pmon performance monitor id[1:28] iclk[1:28] rxclk[1:28] rxd[1:28] tjat digital jitter a ttenuato r esif egress interface transmitter txd[1:28] txclk[1:28] ed[1:28] ctclk* eclk[1:28] rjat digital jitter a ttenuato r tops timing options receiver di agn ost i c l oop b ack 12.5 ds3 loopback modes the temap provides three ds3 m13 multiplexer loopback modes to aid in network and system diagnostics at the ds 3 interface. the ds3 loopbacks can be initiated via the p interface whenever the ds3 framer/m13 multiplexer is enabled. the ds3 master data source register controls the ds3 loopback modes. these loopbacks are also available when the ds3 mux is used with the ds3 mapper via the telecom bus interface. ds3 diagnostic loopback ds3 diagnostic loopback allows the transmitted ds3 stream to be looped back into the receive ds3 path, overriding the ds3 stream received on the rdat/rpos and rneg/rlcv inputs. the rclk signal is also substituted with the transmit ds3 clock, tclk. while this mode is active, ais may be substituted for the ds3 payload being transmitted on the tpos/tdat and tneg/tmfp outputs. the configuration of the receive interface determines how the tneg/tmfp signal is handled during loopback: if the uni bit in the ds3 frmr register is set, then the receive interface is configured for rdat and rlcv, therefore the tneg/tmfp signal is suppressed during loopback so that transmit mfp indications will not be seen nor accumula ted as input lcvs. if the uni bit is clear, then the interface is configured for bipolar signals rpos and rneg,
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 158 therefore the tneg is fed directly to the rneg input. this diagnostic loopback can be used when configured as a multiplexer or as a framer only. the ds3 loopback mode is shown diagrammatically in figure 25. figure 25: ds3 diagnostic loopback diagram ds3 line loopback ds3 line loopbacks allow the received ds3 streams to be looped back into the transmit ds3 paths, overriding the ds3 streams created internally by the multiplexing of the lower speed tributaries. the transmit signals on tpos/tdat and tneg/tmfp are substituted with the receive signals on rpos/rdat and rneg/rlcv. the tclk signal is also substituted with the receive ds3 clock, rclk. while this mode is active, ais may be substituted for the ds3 payload being transmitted on the tpos/tdat and tneg/tmfp outputs. note that the transmit interface must be configured to be the same as the ds3 frmr receive interface for this mode to work properly. the ds3 line loopback mode is shown diagrammatically in figure 26. there is a second form of line loopback which only loops back the ds3 payload. in this mode the ds3 framing overhead is regenerated for the received ds3 stream and then retransmitted. line loopback is selected with the lloop bit in the ds3 master data source register and payload loopback is selected by the ploop bit in the same register.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 159 figure 26: ds3 line loopback diagram ds2 demultiplex loopback ds2 demultiplex loopbacks allow each of t he seven demultiplexed ds2 streams to be looped back into the mx23 and multiplexed up into the transmit ds3 stream. this overrides the tributary ds2 streams coming from the mx12s. the ds2 loopback mode is shown diagrammatically in figure 27 and is enabled via the mx23 loopback activate register. figure 27: ds2 loopback diagram mx12 #7 f r m r mx12 #6 f r m r mx12 #5 f r m r mx12 #4 f r m r mx12 #3 f r m r mx12 #2 f r m r ds3 frmr ds3 tran mx23 mx12 #1 f r m r rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp optional demux ais insertion ds2 tributary loopback path
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 160 12.6 telecom bus mapper/demapper loopback modes the temap provides two loopbacks at t he telecom bus interface to aid in network and system diagnostics at the sonet/sdh interface. these loopback modes can be enabled via the microprocessor whenever the sonet/sdh block is enabled as the mapper for the t1/e1 framer slices or as the mapper for the ds3 framer or m13 multiplexer. telecom diagnostic loopback the telecom bus diagnostic loopback allows the transmitted telecom bus stream to be looped back into the receive sonet/sdh receive path, overriding the data stream received on the telecom drop bus inputs. while telecom diagnostic loopback is active, valid sonet/sdh data continues to be transmitted on the telecom add bus outputs. the entire telecom drop bus is overwritten by the diagnostic loopback even though only one sts-1 spe, stm- 1/vc4 tug3 or stm-1/vc3 is generated by the egress vtpp onto the telecom add bus. this loopback is only available for vt1.5/vt2/tu11/tu12 mapped tributaries. ds3 mapped tributaries must use the ds3 diagnostic loopback. the telecom bus diagnostic loopback mode is shown diagrammatically in figure 28. figure 28: telecom diagnostic loopback diagram vtpp vt/tu payload processor vtpp vt/tu payload processor lddata[7:0] lddp ldpl ldc1j1 ladata[7:0] ladp lapl lac1j1v1 la c 1 rtdm receive tributary demapper telecom line loopback the telecom bus line loopback allows the received telecom drop bus data to be looped back out the telecom add bus after being processed by both the ingress and egress vtpps. both vtpp must be setup for the same sts-1 spe,
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 161 stm-1/vc4 tug3 or stm-1/vc3 otherwise no loopback data will get through. the ingress data path is not affected by the telecom line loopback. this loopback is only available for vt1.5/vt2/tu11/tu12 mapped tributaries. ds3 mapped tributaries must use the ds3 line loopback. the telecom bus line loopback mode is shown diagrammatically in figure 29. figure 29: telecom line loopback diagram vtpp vt/tu payload processor vtpp vt/tu payload processor lddata[7:0] lddp ldpl ldc1j1 ladata[7:0] ladp lapl lac1j1v1 la c 1 rtdm receive tributary path o/h ttop transmit tributary path o/h 12.7 sbi bus data formats the temap uses the scaleable bandwidth interconnect (sbi) bus as a high density link interconnect with devices processing t1s, e1s, ds3s and transparent virtual tributaries. the sbi bus is a multi-point to multi-point bus capable of interconnecting up to three temap devices in parallel with other link layer or tributary processing devices. multiplexing structure the sbi structure uses a locked sonet/sdh structure fixing the position of the tu-3 relative to the sts-3/stm-1. the sbi is also of fixed frequency and alignment as determined by the reference clock (srefclk) and frame indicator signal (sc1fp). frequency deviations are compensated by adjusting the location of the t1/e1/ds3/tvt1.5/tvt2 channels using floating tributaries as determined by the v5 indicator and payload signals (sdv5, sav5, sdpl and sapl). tvts also allow for synchronous operation where sonet/sdh tributary
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 162 pointers are carried within the sbi structure in place of the v5 indicator and payload signals (sdv5, sav5, sdpl and sapl). table 16 shows the bus structure for carrying t1, e1, tvt1.5, tvt2 and ds3 tributaries in a sdh stm-1 like format. up to 84 t1s, 63 e1s, 84 tvt1.5s, 63 tvt2s or 3 ds3s are carried within the octets labeled spe1, spe2 and spe3 in columns 16-270. all other octets are unused and are of fixed position. the frame signal (sc1fp) occurs during the octet labeled c1 in row 1 column 7. the multiplexed links are separated into three synchronous payload envelopes called spe1, spe2 and spe3. each envelope carries up to 28 t1s, 21 e1, 28 tvt1.5s, 21 tvt2s, or a ds3. spe1 carries the t1s numbered 1,1 through 1,28, e1s numbered 1,1 through 1,21 or ds3 number 1,1. spe2 carries t1s numbered 2,1 through 2,28, e1s numbered 2,1 through 2,21 or ds3 number 2,1. spe3 carries t1s numbered 3,1 through 3,28, e1s numbered 3,1 through 3,21 or ds3 number 3,1. tvt1.5s are numbered the same as t1 tributaries and tvt2s are numbered the same as e1 tributaries. the most significant bit in all formats is the first bit of transmission.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 163 table 16 - structure for carrying multiplexed links sbi column 1 6 7 8 15 16 17 18 19 268 269 270 row 1 - - c1 - - spe1spe2spe3spe1 spe1spe2spe3 2 - - - - - spe1spe2spe3spe1 spe1spe2spe3 9 - - - - - spe1spe2spe3spe1 spe1spe2spe3 1 2 3 3 5 6 6 6 7 90 90 90 spe column the temap when enabled for sbi inte rconnection will add and drop either 28 t1s, 21 e1s or a ds3 into one of the three synchronous payload envelopes, spe1, spe2 or spe3. when t1 or e1 tributaries are sourced from the telecom bus via vt1.5, tu11, vt2 or tu12 mappings, the temap also supports a mix of transparent virtual tributaries with t1s and e1s. restriction to this are that only vt1.5s, tu11s and t1s can be mixed together or vt2s, tu12s and e1s can be mixed together. another restriction is that the telecom bus and sbi bus must run from the same clock with a fixed framing offset, ie. srefclk and lrefclk are externally connected. tributary numbering tributary numbering for t1 and e1 uses the spe number, followed by the tributary number within that spe and are numbered sequentially. table 17 and table 18 show the t1 and e1 column numbering and relates the tributary number to the spe column numbers and overall sbi column structure. numbering for ds3 follows the same naming convention even though there is only one ds3 per spe. tvt1.5s and tvt2s follow the same numbering conventions as t1 and e1 tributaries respectively. sbi columns 16-18 are unused for t1, e1, tvt1.5 and tvt2 tributaries. table 17 ? t1/tvt1.5 tributary column numbering t1# spe1 column spe2 column spe3 column sbi column 1 , 1 7 , 35 , 63 19 , 103 , 187 2 , 1 7 , 35 , 63 20 , 104 , 188 3 , 1 7 , 35 , 63 21 , 105 , 189 1 , 2 8 , 36 , 64 22 , 106 , 190 2 , 2 8 , 36 , 64 23 , 107 , 191
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 164 1 , 28 34 , 62 , 90 100 , 184 , 268 2 , 28 34 , 62 , 90 101 , 185 , 269 3 , 28 34 , 62 , 90 102 , 186 , 270 table 18 - e1/tvt2 tributary column numbering e1# spe1 column spe2 column spe3 column sbi column 1 , 1 7 , 28 , 49 , 70 19 , 82 , 145 , 208 2 , 1 7 , 28 , 49 , 70 20 , 83 , 146 , 209 3 , 1 7 , 28 , 49 , 70 21 , 84 , 147 , 210 1 , 2 8 , 29 , 50 , 71 22 , 85 , 148 , 211 2 , 2 8 , 29 , 50 , 71 23 , 86 , 149 , 212 1 , 21 27 , 48 , 69 , 90 79 , 142 , 205 , 268 2 , 21 27 , 48 , 69 , 90 80 , 143 , 206 , 269 3 , 21 27 , 48 , 69 , 90 81 , 144 , 207 , 270 sbi timing master modes the temap supports asynchronous sbi timing modes. asynchronous modes allow t1, e1, ds3 and transparent tributaries to float within the sbi structure to accommodate differences in timing. in asynchronous modes timing is communicated across the scaleable bandwidth interconnect by floating data structures within the sbi. payload indicator signals in the sbi control the position of the floating data structure and therefore the timing. when sources are running faster than the sbi the floating payload structure is advanced by an octet be passing an extra octet in the v3 octet locations (h3 octet for ds3 mappings). when the source is slower than the sbi bus, the floating payload is retarded by leaving the octet after the v3 or h3 octet unused. both these rate adjustments are indicated by the sbi control signals. transparent vts (tvts) can float in the sbi structure in two ways. the first method uses valid v1 and v2 pointers to indicate positive and negative pointer justifications. the second methods uses the sbi signals sdv5, sav5, sdpl and sapl to indicate rate adjustments. in the drop bus the temap will always provide both valid pointers with valid sdv5 and sdpl signals. on the sbi add bus the temap needs to be configured on a per tributary basis for either transparent vt mode. transparent vt operation is configured on a per tributary basis via the etvt and etvtptrdis bits in the ttmp tributary control registers. note that the sc1fpen bit in register 1209h (sonet/sdh master ds3 clock generation control) must be set appropriately for tvt mode.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 165 on the drop bus the temap is timing master as determined by the arrival rate of data over the sbi. on the add bus the temap can be either the timing master or the timing slave. when the temap is the timing slave it receives its transmit timing information from the arrival rate of data across the sbi add bus. when the temap is the timing master it signals devices on the sbi add bus to speed up or slow down with the justification request signal, sajust_req. the temap as timing master indicates a speedup request to a link layer sbi device by asserting the justification request signal high during the v3 or h3 octet. when this is detected by the link layer it will speed up the c hannel by inserting extra data in the next v3 or h3 octet. the temap indicates a slowdown request to the link layer by asserting the justification request signal high during the octet after the v3 or h3 octet. when detected by the link layer it will retard the channel by leaving the octet following the next v3 or h3 octet unused. both advance and retard rate adjustments take place in the frame or multi-frame following the justification request. sbi link rate information the temap sbi bus provides a method for carrying link rate information between devices. this is optional on a per channel basis. two methods are specified, one for t1 and e1 channels and the second for ds3 channels. link rate information is not available for tvts. these methods use the reference 19.44mhz sbi clock and the sc1fp frame synchronization signal to measure channel clock ticks and clock phase for transport across the bus. the t1 and e1 method allows for a count of the number of t1 or e1 rising clock edges between 2 khz sc1fp frame pulses. this count is encoded in clkrate[1:0] to indicate that the nom inal number of clocks, one more than nominal or one less than nominal should be generated during the sc1fp period. this method also counts the number of 19.44mhz clock rising edges after sampling sc1fp high to the next rising edge of the t1 or e1 clock, giving the ability to control the phase of the generated clock. the link rate information passed across the sbi bus via the v4 octet and is shown in table 19. table 20 shows the encoding of the clock count, clkrate[1:0], passed in the link rate octet. table 19: sbi t1/e1 link rate information sc1fp
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 166 srefclk t1/e1 clk clock count phase link rate octet bit # 7 6 5:4 3:0 t1/e1 format alm 0 clkrate[1:0] phase[3:0] table 20: sbi t1/e1 clock rate encoding clkrate[1:0] t1 clocks / 2khz e1 clocks / 2 khz ?00? ? nominal 772 1024 ?01? ? fast 773 1025 ?1x? ? slow 771 1023 the method for transferring ds3 link rate information across the sbi passes the encoded count of ds3 clocks between 2khz sc1fp pulses in the same method used for t1/e1 tributaries, but does not pass any phase information. the other difference from t1/e1link rate is that clkrate[1:0] indicates whether the nominal number of clocks are generat ed or if four fewer or four extra clocks are generated during the sc1fp period. the format of the ds3 link rate octet is shown in table 21. this is passed across the sbi via the linkrate octet which follows the h3 octet in the column, see table 25. table 22 shows the encoding of the clock count, clkrate[1:0], passed in the link rate octet. table 21: ds3 link rate information link rate octet bit # 7 6 5:4 3:0 ds3 format 0 0 clkrate[1:0] unused
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 167 table 22: ds3 clock rate encoding clkrate[1:0] ds3 clocks / 2khz ?00? ? nominal 22368 ?01? ? fast 22372 ?1x? ? slow 22364 sbi alarms the temap transfers alarm conditions across the sbi bus for t1 and e1 tributaries. the temap does not support alarm conditions across the sbi bus for ds3 nor transparent vts. table 19 show the alarm indication bit, alm, as bit 7 of the link rate octet. devices connecting to the temap which do not support alarm indications must set this bit to 0 on the sbi add bus. the presence of an alarm condition is indicated by the alm bit set high in the link rate octet. the absence of an alarm condition is indicated by the alm bit set low in the link rate octet. in the egress direction the temap can be configured to use the alarm bit to force ais on a per link basis. t1 tributary mapping table 23 shows the format for mapping 84 t1s within the spe octets. clear channel bits within each t1 are easily located within this mapping. the v1, v2 and v4 octets are not used to carry t1 data and are either reserved or used for control across the interface. when enabled, the v4 octet is the link rate octet of tables 1 and 3. it carries alarm and clock phase information across the sbi bus. the v1 and v2 octets are unused and should be ignored by devices listening to the sbi bus. the v5 and r octets do not carry any information and are fixed to a zero value. the v3 octet carries a t1 data octet but only during rate adjustments as indicated by the v5 indicator signals, dv5 and av5, and payload signals, sdpl and sapl. the v1, v2, v3 and v4 octets are fixed to the locations shown. all the other octets, shown shaded for t1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2khz multi-frame. the position of the floating t1 is identified via the v5 indicator signals, sdv5 and sav5, which locate the v5 octet. when the t1 tributary rate is faster than the sbi nominal t1 tributary rate, the t1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the v3 location. when the t1 tributary rate is slower than the nominal sbi tributary rate the t1 tributary is
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 168 shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the v3 octet and delaying the octet that was originally in that position. table 23 - t1 framing format col # t1#1,1 t1#2,1-3,28 t1#1,1 t1#2,1-3,28 t1#1,1 t1#2,1-3,28 row # 1-18 19 20-102 103 104-186 187 188-270 1 unused v1 v1 v5 - ppssssir - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v2 v2 r - ppssssir - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v3 v3 r - ppssssir - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v4 v4 r - ppssssir - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 169 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - the p 1 p 0 s 1 s 2 s 3 s 4 ir octet carries one bit of the clear channel t1 stream in the i bit. the r, p and s bits are unused. t1 tributary asynchronous timing is compensated via the v3 octet. t1 tributary link rate adjustments are optionally passed across the sbi via the v4. t1 tributary alarm conditions are optionally passed across the sbi bus via the link rate octet in the v4 location. e1 tributary mapping table 24 shows the format for mapping 63 clear channel e1s within the spe octets. the i bits carry the clear channel e1 bits. the v1, v2 and v4 octets are not used to carry e1 data and are either reserved or used for control information across the interface. when enabled, the v4 octet carries clock phase information across the sbi. the v1 and v2 octets are unused and should be ignored by devices listening to the sbi bus. the v5 and r octets do not carry any information and are fixed to a zero value. the v3 octet carries an e1 data octet but only during rate adjustments as indicated by the v5 indicator signals, sdv5 and sav5, and payload signals, sdpl and sapl. the v1, v2, v3 and v4 octets are fixed to the locations shown. all the other octets, shown shaded for e1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2khz multi-frame. the position of the floating e1 is identified via the v5 indicator signals, sdv5 and sav5, which locate the v5 octet. when the e1 tributary rate is faster than the e1 tributary nominal rate, the e1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the v3 location. when the e1 tributary rate is slower than the nominal rate the e1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the v3 octet and delaying the octet that was originally in that position. table 24 ? e1 framing format col # e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 row # 1-18 19 20-81 82 83-144 145 146-207 208 209-270 1 unused v1 v1 v5 - pp - i - 2 unused i - i - i - i -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 170 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - r - 1 unused v2 v2 r - pp - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - r - 1 unused v3 v3 r - pp - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - r - 1 unused v4 v4 r - pp - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - r - e1 tributary asynchronous timing is compensated via the v3 octet. e1 tributary link rate adjustments are optionally passed across the sbi via the v4 octet. e1 tributary alarm conditions are optionally passed across the sbi bus via the link rate octet in the v4 location.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 171 note that itu-t g.747 mutiplexed e1 streams are not supported over the sbi interface. this e1 mode of operation is restricted to using the serial clock and data system interface. ds3 tributary mapping table 25 shows a ds3 tributary mapped within the first synchronous payload envelope spe1. the v5 indicator pulse identifies the v5 octet. the ds3 framing format does not follow an 8khz frame period so the floating ds3 multi-frame located by the v5 indicator, shown in heavy border grey region in table 25, will jump around relative to the h1 frame on ev ery pass. in fact the v5 indicator will often be asserted twice per h1 frame, as is shown by the second v5 octet in table 25. the v5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the h3 octet or leaving empty the octet after the h3 octet. table 25 - ds3 framing format spe col # ds3 1 ds3 2-56 ds3 57 ds3 58-84 ds3 col 85 row sbi col# 1,4,7,10 13 16 184 268 1 unused h1 v5 ds3 ds3 ds3 ds3 2 unused h2 ds3 ds3 ds3 ds3 ds3 3 unused h3 ds3 ds3 ds3 ds3 ds3 4 unused linkrate ds3 ds3 ds3 ds3 ds3 5 unused unused ds3 ds3 ds3 ds3 ds3 6 unused unused ds3 ds3 ds3 ds3 ds3 7 unused unused ds3 ds3 ds3 ds3 ds3 8 unused unused ds3 ds3 v5 ds3 ds3 9 unused unused ds3 ds3 ds3 ds3 ds3 because the ds3 tributary rate is less than the rate of the grey region, padding octets are interleaved with the ds3 tributary to make up the difference in rate. interleaved with every ds3 multi-frame are 35 stuff octets, one of which is the v5 octet. these 35 stuff octets are spread evenly across seven ds3 subframes. each ds3 subframe is eight blocks of 85 bits. the 85 bits making up a ds3 block are padded out to be 11 octets. table 26 shows the ds3 block 11 octet format where r indicates a stuff bit, f indicates a ds3 framing bit and i indicates ds3 information bits. table 27 shows the ds3 multi-frame format that is packed into the grey region of table 25. in this table v5 indicates the v5 octet which is also a stuff octet, r indicates a stuff octet and b indicates the 11 octet ds3 block. each row in table 27 is a ds3 multi-frame. the ds3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after the v5 octet is added every sixth frame.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 172 table 26 - ds3 block format octet # 1 2 3 4 5 6 7 8 9 10 11 data rrrfiiii 8*i 8*i 8*i 8*i 8* i 8*i 8*i 8*i 8*i 8*i table 27 - ds3 multi-frame stuffing format v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b ds3 asynchronous timing is compensated via the h3 octet. ds3 link rate adjustments are optionally passed across the sbi via the linkrate octet. transparent vt1.5/tu11 mapping vt1.5 and tu11 virtual tributaries, tvt1.5s, are transported across the sbi bus in a similar manner to the t1 tributary mapping. table 28 shows the transparent structure where ?i? is used to indicate information bytes. there are two options when carrying virtual tributaries on the sbi bus, the primary difference being how the floating v5 payload is located. the first option is locked tvt mode which carries the entire vt1.5/tu11 virtual tributary indicated by the shaded region in table 28. locked is used to indicate that the location of the v1,v2 pointer is locked. the virtual tributary must have a valid v1,v2 pointer to locate the v5 payload. in this mode the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, may be generated but must be ignored by the receiving device. in locked mode timing is always sourced by the transmitting side, therefore justification requests are not used and the sajust_req signal is ignored. other than the v1 and v2 octets which must carry valid pointers, all octets can carry data in any format. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 28. the second option is floating tvt mode which carries the payload comprising the v5 and i octets within the shaded region of table 28. in this mode the v1,v2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, must be valid and are used to locate the floating payload. (i.e. sdv5/sav5 are high during the v5 octet, and sdpl/sapl are high during all
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 173 shaded bytes except the v1/v2/v4 octets and the v3 octet or the octet after v3 depending on pointer movements.) the justification request signal can be used to control the timing on the add bus. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 28. the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 28 - transparent vt1.5/tu11 format col # vt1.5#1,1 #2,1-3,28 vt1.5#1,1 #2,1-3,28 vt1.5#1,1 #2,1-3,28 row # 1-18 19 20-102 103 104-186 187 188-270 1 unused v1 v1 v5 - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v2 v2 i - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v3 v3 i - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v4 v4 i - i - 2 unused i - i - i - 3 unused i - i - i -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 174 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - transparent vt2/tu12 mapping vt2 and tu12 virtual tributaries, tvt2s, are transported across the sbi bus in a similar manner to the e1 tributary mapping. the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 29 shows the transparent structure where ?i? is used to indicate information bytes. there are two options when carrying virtual tributaries on the sbi bus, the primary difference being how the floating v5 payload is located. the first option is locked tvt mode which carries the entire vt2/tu12 virtual tributary indicated by the shaded region in table 29. the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. locked is used to indicate that the location of the v1,v2 pointer is locked. the virtual tributary must have a valid v1,v2 pointer to locate the v5 payload. in this mode the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, are optionally generated but must be ignored by the receiving device. in locked mode timing is always sourced by the transmitting side, therefore justification requests are not used and the sajust_req signal is ignored. other than the v1 and v2 octets which are carrying valid pointers, all octets can carry data in any format. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 29. the second option is floating tvt mode which carries the payload comprised of the v5 and i octets within the shaded region of the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 29. the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. in this mode the v1,v2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, must be valid and are used to locate the floating payload. (i.e. sdv5/sav5 are high during the v5 octet, and sdpl/sapl are high
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 175 during all shaded bytes except the v1/v2/v4 octets and the v3 octet or the octet after v3 depending on pointer movements.) the justification request signal can be used to control the timing on the add bus. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 29. the temap supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 29 ? transparent vt2/tu12 format col # e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 row # 1-18 19 20-81 82 83-144 145 146-207 208 209-270 1 unused v1 v1 v5 - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v2 v2 i - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v3 v3 i - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v4 v4 i - i - i -
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 176 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 12.8 serial clock and data format the serial clock and data interfaces are able to carry the complete payload for 28 t1s or 21 e1s. each t1 or e1 is assigned to two transmit pins and two receive data pins for the payload and clock. in t1 mode, all 28 pairs of clock and data pins are used in each direction. in normal e1 mode, the first 21 pairs of clock and data pins are used in each direction. the clock and data pins numbered between 22 and 28 are not defined, as the 22 nd through 28 th pmon blocks are not used in this mode. in itu-t g.747 mutiplexed e1 mode, every fourth set of clock and data pins are not used in each direction. (i.e. pins 1-3, 5-7, 9-11, 13-15, 17-19, 21-23, 25-27 are defined while pins 4, 8, 12, 16, 20, 24, and 28 are not defined.) this is because the 4 th , 8 th , 12 th , 16 th , 20 th , 24 th and 28 th pmon blocks are not used in this mode. 12.9 prgd pattern generation the pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in figure 30 below: figure 30: prgd pattern generator
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 177 the pattern generator consists of a 32 bit shift register and a single xor gate. the xor gate output is fed into the first stage of the shift register. the xor gate inputs are determined by values written to the length register (pl[4:0]) and the tap register (pt[4:0], when the ps bit is low). when ps is high, the pattern detector functions as a recirculating shift register, with length determined by pl[4:0]. generating and detecti ng repetitive patterns when a repetitive pattern (such as 1-in-8) is to be generated or detected, the ps bit must be set to logic 1. the pattern length register must be set to (n-1), where n is the length of the desired repetitive pattern. several examples of programming for common repetitive sequences are given below in the common test patterns section. for pattern generation, the desired pattern must be written into the prgd pattern insertion registers. the repet itive pattern will then be continuously generated. the generated pattern will be inserted in the output data stream, but the phase of the pattern cannot be guaranteed. for pattern detection, the prgd will determine if a repetitive pattern of the length specified in the pattern length register exists in the input stream. it does so by loading the first n bits from the data stream, and then monitoring to see if the pattern loaded repeats itself error free fo r the subsequent 48 bit periods. it will repeat this process until it finds a repetitive pattern of length n, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. note that the prgd does not look for the pattern loaded into the pattern insertion registers, but rather automatically detects any repetitive pattern of the specified length. the precise pattern detected can be determined by initiating a prgd update, setting pdr[1:0] = 00 in the prgd control register, and reading the pattern detector registers (which will then contain the 32 bits detected immediately prior to the strobe). common test patterns the prgd can be configured to monitor the standardized pseudo random and repetitive patterns described in itu-t o.151. the register configurations required to generate these patterns and others are indicated in table 30 and table 31 below:
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 178 table 30: pseudo random patte rn generation (ps bit = 0) pattern type tr lr ir#1 ir#2 ir#3 ir#4 tinv rinv 2 3 -1 00 02 ff ff ff ff 0 0 2 4 -1 00 03 ff ff ff ff 0 0 2 5 -1 01 04 ff ff ff ff 0 0 2 6 -1 04 05 ff ff ff ff 0 0 2 7 -1 00 06 ff ff ff ff 0 0 2 7 -1 (fractional t1 lb a ctivate) 03 06 ff ff ff ff 0 0 2 7 -1 (fractional t1 lb deactivate) 03 06 ff ff ff ff 1 1 2 9 -1 (o.153) 04 08 ff ff ff ff 0 0 2 10 -1 02 09 ff ff ff ff 0 0 2 11 -1 (o.152, o.153) 08 0a ff ff ff ff 0 0 2 15 -1 (o.151) 0d 0e ff ff ff ff 1 1 2 17 -1 02 10 ff ff ff ff 0 0 2 18 -1 06 11 ff ff ff ff 0 0 2 20 -1 (o.153) 02 13 ff ff ff ff 0 0 2 20 -1 (o.151 qrss bit=1) 10 13 ff ff ff ff 0 0 2 21 -1 01 14 ff ff ff ff 0 0 2 22 -1 00 15 ff ff ff ff 0 0 2 23 -1 (o.151) 11 16 ff ff ff ff 1 1 2 25 -1 02 18 ff ff ff ff 0 0 2 28 -1 02 1b ff ff ff ff 0 0 2 29 -1 01 1c ff ff ff ff 0 0 2 31 -1 02 1e ff ff ff ff 0 0
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 179 table 31: repetitive pattern generation (ps bit = 1) pattern type tr lr ir#1 ir#2 ir#3 ir#4 tinv rinv all ones 00 00 ff ff ff ff 0 0 all zeros 00 00 fe ff ff ff 0 0 alternating ones/zeros 00 01 fe ff ff ff 0 0 double alternating ones/zeros 00 03 fc ff ff ff 0 0 3 in 24 00 17 22 00 20 ff 0 0 1 in 16 00 0f 01 00 ff ff 0 0 1 in 8 00 07 01 ff ff ff 0 0 1 in 4 00 03 f1 ff ff ff 0 0 inband loopback activate 00 04 f0 ff ff ff 0 0 inband loopback deactivate 00 02 fc ff ff ff 0 0 notes for the pseudo random and repetitive pattern generation tables 1. the ps bit and the qrss bit are contained in the prgd control register 2. tr = prgd tap register 3. lr = prgd length register 4. ir#1 = prgd pattern insertion #1 register 5. ir#2 = prgd pattern insertion #2 register 6. ir#3 = prgd pattern insertion #3 register 7. ir#4 = prgd pattern insertion #4 register 8. the tinv bit and the rinv bit are contained in the prgd control register 12.10 jtag support the temap supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 180 standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below. figure 31: boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 181 bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register placed in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi, and forced onto all digital outputs. 12.10.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 182 figure 32: tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 183 test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 184 update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. boundary scan instructions the following is a description of the standard instructions. each instruction selects a serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 185 stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out of the output, tdo, using the shift-dr state. boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table in the jtag test port section 11.2. figure 33: input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 186 figure 34: output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit figure 35: bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 187 figure 36: layout of output en able and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 188 13 functional timing 13.1 ds3 line side interface timing all functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the temap registers are set to their default states). figure 37: receive bipolar ds3 stream rpos rneg 3 consec 0s lcv rclk the receive bipolar ds3 stream diagram (figure 37) shows the operation of the temap while processing a b3zs encoded ds3 stream on inputs rpos and rneg. it is assumed that the first bipolar violation (on rneg) illustrated corresponds to a valid b3zs signature. a line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid b3zs signature. figure 38: receive unipolar ds3 stream rclk rdat x1 bit rlcv x2 bit info 84 c bit info 1 info 2 info 3 info 4 info 5 orpormbit orfbit info 84 info 1 lcv indication the receive unipolar ds3 stream diagram (figure 38) shows the complete ds3 receive signal on the rdat input. line code violation indications, detected by an upstream b3zs decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon line code violation event counter is incremented each time a logic 1 is sampled on rlcv.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 189 figure 39: transmit bipolar ds3 stream tcl k tpos tneg ticlk 11 0 01 0 0 the transmit bipolar ds3 st ream diagram (figure 39) illustrates the generation of a bipolar ds3 stream. the b3zs encoded ds3 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a ds3 line interface unit. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 40: transmit unipolar ds3 stream tclk tdat nib 1 bit 4 tmfp ticlk x1 x1 nib 1 bit 4 nib 1190 bit 1 nib 22 bit 4 x2 nib 21 bit 1 the transmit unipolar ds3 stream diagram (figure 40) illustrates the unipolar ds3 stream generation. the tmfp output marks the m-frame boundary, x1 bit, in the transmit stream. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 190 13.2 ds3 system side interface timing figure 41: framer mode ds3 transmit input stream tdati info 84 tfpi/tmfpi info 84 info 83 info 82 x1 info 2 info 1 x2 info 1 info 2 info 3 info 84 info 82 info 83 f4 info 82 info 83 tfpo/tmfpo ticlk or rcl k figure 42: framer mode ds3 transmit input stream with tgapclk tgapclk tdati info 1 info 83 info 82 info 81 info 3 info 2 info 2 info 3 info 4 info 1 info 83 info 84 info 83 info 84 info 1 the framer mode ds3 transmit input stream diagram (figure 41) shows the expected format of the inputs tdati and tfpi/tmfpi along with ticlk and the output tfpo/tmfpo when the opmode[1:0] bits are set to ?ds3 framer only mode? in the global configuration register. if the txmfpi bit in the ds3 master unchannelized interface options register is logic 0, then tfpi is valid, and the temap will expect tfpi to pulse for every ds3 overhead bit with alignment to tdati. if the txmfpi register bit is logic 1, then tmfpi is valid, and the temap will expect tmfpi to pulse once every ds3 m-frame with alignment to tdati. if the txmfpo bit in the ds3 master unchannelized interface options register is logic 0, then tfpo is valid, and the temap will pulse tfpo once every 85 ticlk cycles, providing upstream equipment with a reference ds3 overhead pulse. if the txmfpo register bit is logic 1, then tmfpo is valid and the temap will pulse tmfpo once every 4760 ticlk cy cles, providing upstream equipment with a reference m-frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. when the ds3 interface is loop timed by setting the loopt bit in the ds3 master data source register, rclk replaces ticlk as the transmit timing reference and all timing is relative to rclk. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the ds3 master unchannelized interface options register is set to logic 1, as in figure 42. tgapclk remains high during the overhead bit positions. tdati is sampled on the active edge of tgapclk when txgapen is set to logic 1 and on the active edge of ticlk when txgapen is set to logic 0. the tdatifall bit in the ds3 master unchannelized interface options register selects the active edge of ticlk or tgapclk for sampling tdati.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 191 figure 43: framer mode ds3 receive output stream rdato info 84 rfpo/rmfpo info 84 info 83 info 82 x 1 info 2 info 1 x 2 info 1 info 2 info 3 info 84 info 82 info 83 f 4 info 82 info 83 rovrhd rsclk figure 44: framer mode ds3 receive output stream with rgapclk rgapclk rdato info 84 info 84 info 83 info 82 info 2 info 1 info 1 info 2 info 3 info 84 info 82 info 83 info 82 info 83 the ds3 framer only mode receive output stream diagram (figure 43) shows the format of the outputs rdato, rfpo/rmfpo, rsclk rovrhd when the opmode[1:0] bits are set to ?ds3 framer only mode? in the global configuration register. figure 43 shows the data streams when the temap is configured for the ds3 receive format. if the rxmfpo bit in the ds3 master unchannelized interface options register is logic 0, rfpo is valid and will pulse high for one rsclk cycle on first bit of each m-subframe with alignment to the rdato data stream. if the rxmfpo register bit is a logic 1 (as shown figure 43), rmfpo is valid and will pulse high on the x1 bit of the rdato data output stream. rovrhd will be high for ever y overhead bit position on the rdato data stream. figure 44 shows the output data stream with rgapclk in place of rsclk when the rxgapen bit in the ds3 master unchannelized interface options register set to logic 1. rgapclk remains high during the overhead bit positions. 13.3 telecom drop bus interface timing figure 45 shows the function of the various telecom drop bus signals in au3 mode. data on lddata[7:0] is sampled on the rising edge of lrefclk. the bytes forming the three sts-1 synchronous payload envelopes are identified when the ldpl signal is high. in this diagram, a negative stuff event is shown occurring on sts-1 #2 and a positive stuff event on sts-1 #3. the ldc1j1v1 signal pulses high, while ldpl is set low, to mark the c1 byte of the first sts-1 in every frame of the sts-3 transport envelope. the ldc1j1v1 signal is high when the ldpl signal is high to mark every j1 byte of each of the three sts-1
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 192 spes. the bytes forming the various tributary synchronous payload envelopes are identified by the ldtpl when set high. the ldv5 signal pulses high to mark the v5 bytes of each outgoing tributaries. ldtpl and ldv5 are invalid when ldpl is set low. the three sts-1 spes can each have different alignments to the sts-3 transport envelope and the alignment is changing for two of the sts-1 spes (sts-1 #2 and #3) due to the pointer justification events shown. figure 45: telecom drop bus timing - sts-1 spes / au3 vcs ???? ldpl lrefclk ldc1j1 ldv5 invalid invalid iv iv ldtpl invalid invalid iv iv sts-1 #1 spe j1 byte lddata[7:0] a 1 a 1 a 2 a 2 a 2 c1c1c1 a 1 h1 h1 h2 h2 h2 h3 h3 h1 negative stuff for sts-1 #2 spe which happens to carry a non-final h4 byte v5 byte as marked by otv5 positive stuff for sts-1 #3 spe j1 h4 v x v5 any v1 - v4 byte tu#1, sts-1 #1 last h4 byte in tributary multiframe h4 c2 g1 the ldv5 and ldtpl signals are optional when using the ingress vtpp within the temap which will regenerate the ld v5 and ldtpl signals from ldc1j1v1, ldpl and the pointers within lddata[7:0]. in order to bypass the ingress vtpp, the data on the telecom drop bus must be locked such that all three sts-1 spes are aligned to the sts-3 transport envelope with the j1 bytes immediately following the c1 bytes. this is shown in figure 46.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 193 figure 46: telecom drop bus timing - locked sts-1 spes / au3 vcs lrefclk ldc1j1 ldpl ???? ldtpl ldv5 implicit location of sts-1 spe j1 bytes lddata[7:0] a 2c1c1c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff events possible v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 figure 47 shows the function of the various telecom drop bus signals in au4 mode. data on lddata [7:0] is sampled on the rising edge of lrefclk. the bytes forming the vc4 virtual container are identified by the setting the ldpl signal high. the ldc1j1v1 signal pulses high, while ldpl is set low, to mark the single c1 byte in every frame of the au4 transport envelope. the ldc1j1v1 signal is set high again with ldpl high to mark the j1 byte of the vc4. the bytes forming the various tributary synchronous payload envelopes are identified by the ldtpl signal being set high. the ldv5 signal pulses high to mark the v5 bytes of each outgoing tributaries.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 194 figure 47: telecom drop bus timing - au4 vc lrefclk ???? ldpl ldc1j1 lddat a [7:0] a1 a2 a2 a2 c1 x x v5 byte tug3 #1 national bytes v5 j1 v1 v1 v1 v1 byte tu #1, tug2 #1, tug3 #1 np np np first npi byte tug3 #1 j1 byte vc4 z7 z7 byte tug3 #1 ldt pl invalid ldv5 invalid the ldv5 and ldtpl signals are optional when using the ingress vtpp within the temap which will regenerate the ld v5 and ldtpl signals from ldc1j1v1, ldpl and the pointers within lddata[7:0]. in order to bypass the ingress vtpp, the position of the single j1 byte and the vc4 is implicitly defined by the c1 byte position. in the locked au4 mode, the vc4 is defined to be aligned to the au4 transport envelope such that the j1 byte occupies the first available payload byte after the c1 byte, and no pointer justifications are possible. 13.4 telecom add bus interface timing figure 48 shows the function of the telecom add bus signals in au3 mode. data on ladata[7:0] is updated on the rising edge of lrefclk. the lac1 input is sampled on the rising edge of lrefclk and aligns all devices on the add bus by marking the first c1 byte of the first sts-1 in every fourth sts-3 transport envelope. lac1 pulses every fourth sts-3 to indicate tributary multiframe alignment on the add bus. the bytes forming the three sts-1 synchronous payload envelopes are identified when the lapl signal is high. the lac1j1v1 signal pulses high, while lapl is set low, to mark the c1 byte of the first sts-1 in every frame of the sts-3 transport envelope. the lac1j1v1 signal is high when the lapl signal is high to mark every j1 byte of each of the three sts-1 spes. the three sts-1 spes are fixed at two different alignments to the sts-3 transport envelope. the first is shown in figure 48 in which the j1 bytes follow immediately after the c1 bytes. the second alignment is at spe pointer location zero where the j1 bytes follow immediately after the h3 bytes.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 195 the lac1 signal is updated on the rising edge of lrefclk. it is output during when the temap is outputing valid tributary data onto the add bus. it is asserted high for all bytes making up a tributary and is asserted low during overhead bytes. figure 48: output bus timing - locked sts-1 spes / au3 vcs lrefclk ???? lac1 lac1j1v1 lapl implicit location of sts-1 spe j1 bytes ladata[7:0] a 2c1 c1c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff events possible v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 laoe figure 49 shows the function of the temap telecom add bus when operating in au4 mode. in au4 mode, the position of the single j1 byte and the vc4 is implicitly defined by the lac1 byte position. the vc4 is defined to be aligned to the au4 transport envelope such that the j1 byte occupies the first available payload byte after the c1 byte. no pointer justification events take place on the add bus. lac1j1v1 pulses high to mark the first c1 byte, the j1 byte and the third byte after j1 of the first tributary in the au4 stream. lapl identifies the payload bytes on ladatad[7:0].
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 196 figure 49 - output bus timing - locked au4 vc case lrefcl k ???? lac1 laoe lapl lac1j1v1 implicit location of vc4 j1 byte ladata[7:0] a 2c1 x x h4 j1 national bytes first r column of tug3 #1 v5 v1 v1 byte tu #1, tug2 #1, tug3 #1 last h4 byte in tributary multiframe v5 byte tu #1, tug2 #1, tug3 #1 fixed stuff columns rrrrrr r rrr rr z6 z6 byte tu #1, tug2 #1, tug3 #3 13.5 sonet/sdh serial alarm port timing the timing relationships of the signals related to the remote serial alarm port are shown in figure 50. the remote se rial alarm port cl ocks, radeastck and radwestck, are nominally 9.72 mhz clo cks but can range from 1.344 mhz to 10 mhz. the remote serial alarm port frame pulses, radeastfp and radwestfp, mark the first bip-2 error bit (b1 in figure 50) of the first tributary (tu #1 of tug2 #1, tug3 #1) on radeast and radwest, respectively. the frame pulses must be set high to mark every first bip-2 error bit of the first tributary. tributaries on radeast and radwest are arranged in the order of transmission of an stm-1 stream as defined in the references. i.e., tu #1 of tug2 #1 in tug3 #1, tu#1 of tug2 #1 in tug3 #2, tu#1 of tug2 #1 in tug3 #3, tu#1 of tug2 #2 in tug3 #1, ... tu #1 of tug2 #7 in tug3 #3, tu #2 of tug2 #1 in tug3 #1, ... tu #2 of tug2 #7 in tug3 #3, tu #3 of tug2 #1 in tug3 #1, ... tu #4 of tug2 #7 in tug3 #3. timeslot assignment on radeast and radwest is unrelated to the configuration of the tug2. timeslots are always reserved for four tributaries in every tug2 even if it is configured for tributaries with higher bandwidth than tu11, such as tu12. at timeslots devoted to non-existent tributaries, for example, tributary 4 of a tug2 configured for tu12, radeast and radwest will be ignored.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 197 each tributary in the remote serial alarm port is allocated eight timeslots. the first two timeslots, labeled b1 and b2 in figure 50, reports the two possible bip-2 errors in the tributary payload frame. an alarm contributing to remote defect indications is reported in the third timeslot and is labeled d in figure 50. the timeslot labeled f report alarms contributing to remote failure indications. in extended rdi mode, the d and f bits are considered as two bit codepoint and will be reported on the rdi and rfi signal s. out of extended rdi mode, the d and f bits are independent. the remaining four timeslots are unused and are ignored. figure 50: remote serial alarm port timing radeastfp/ radwestfp x radeast/ radwest b1 b2 d f x x xx b1 b2 df xx xx b1 b2 df xx xx b1 b2 df x xx tu #1, tug2 #1, tug3 #1 tu #1, tug2 #1, tug3 #2 tu #1, t ug2 #1, tug3 #3 tu #1, tug2 #2, tug3 #1 radeastfp/ radwestfp ... tu #1, tug 2 #1 tug3 #1 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tu #1, tug2 #2 tug2 #3 tu #4, tug 2 #7 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tug3 #3 x tug2 #6 x radeastck/ radwestck radeastck/ radwestck
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 198 13.6 sbi drop bus interface timing figure 51: sbi drop bus t1/e1 functional timing c1 v3 v3 v3 byte#4. v5 byte#9. srefcl k sc1fp sddata[7:0] sdpl sdv5 sddp sbiact figure 51 illustrates the operation of the sbi drop bus, using a negative justification on the second to last v3 octet as an example. the justification is indicated by asserting sdpl high during the v3 octet. the timing diagram also shows the location of one of the tributaries by asserting sdv5 high during the v5 octet. the sbiact signal is shown for the case in which temap is driving spe#1 onto the sbi drop bus. figure 52: sbi drop bus ds3 functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 srefcl k sc1fp sddata[7:0 ] sdpl sdv5 sddp sbiact figure 52 shows three ds-3 tributaries mapped onto the sbi bus. a negative justification is shown for ds-3 #2 during the h3 octet with sdpl asserted high. a positive justification is shown for ds-3#1 during the first ds-3#1 octet after h3 which has sdpl asserted low. the sbiact signal is shown for the case in which temap is driving spe#2 (ds-3#2) onto the sbi drop bus.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 199 13.7 sbi add bus interface timing the sbi add bus functional timing for the transfer of tributaries whether t1/e1 or ds3 is the same as for the sbi drop bus. the only difference is that the sbi add bus has one additional signal: the sajust_req output. the sajust_req signal is used to by the temap in sbi master timing mode to provide transmit timing to sbi link layer devices. figure 53: sbi add bus justif ication request functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 srefclk sc1fp sadata[7:0] sapl sav5 sadp sajust_req figure 53 illustrates the operation of the sbi add bus, using positive and negative justification requests as an example. (the responses to the justification requests would take effect during the next multi-frame.) the negative justification request occurs on the ds-3#3 tributary when sajust_req is asserted high during the h3 octet. the positive justification occurs on the ds-3#2 tributary when sajust_req is asserted high during the first ds-3#2 octet after the h3 octet. 13.8 egress serial clock and data interface timing by convention in the following functional timing diagrams, the first bit transmitted in each channel shall be designated bit 1 and the last shall be designated bit 8. each of the ingress and egress master and clock modes apply to both t1 and e1 configurations with the exception of the 2.048mhz t1 clock slave modes. figure 54: t1 and e1 egress interface clock master: clear channel mode 1234567812345678123456 78 ec l k [x] ed[x] 8
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 200 the egress interface is configured for the clock master: clear channel mode by writing to emode[2:0] in thet1/e1 egress serial interface mode select register. ed[x] is sampled on the rising edge of the eclk[x] output. when the the ede bit in the t1/e1 serial interface configuration register is set to logic 0, then ed[x] is sampled on the falling edge of eclk[x], and the functional timing is described by figure 54 with the eclk[x] signal inverted. figure 55: t1 and e1 egress interface clock slave: clear channel mode 1234567812345678123456 78 ec l k [x] ed[x] 8 the egress interface is configured for the clock slave: clear channel mode by writing to emode[2:0] in thet1/e1 egress serial interface mode select register. ed[x] is clocked in on the rising edge of the eclk[x] input. when the ede bit in the t1/e1 serial interface configuration register is set to logic 0, then ed[x] is sampled on the falling edge of eclk[x], and the functional timing is described by figure 55 with the eclk[x] signal inverted. 13.9 ingress serial clock and data interface timing figure 56: t1 and e1 ingress interface clock master: clear channel mode 1234567812345678123456 78 icl k [x] id[x] 8 the ingress interface is configured for the clock slave: clear channel mode by writing to imode[1:0] in the t1/e1 ingress serial interface mode select register. id[x] is updated on the falling edge of the iclk[x] input. when the ide bit in the t1/e1 serial interface configuration register is set to logic 1, then id[x] is updated on the rising edge of iclk[x], and the functional timing is described by figure 56 with the iclk[x] signal inverted.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 201 14 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 32 - absolute maximum ratings parameter symbol value units ambient temperature under bias -40 to +85 c storage temperature t st -40 to +125 c supply voltage v dd2.5 -0.3 to + 3.5 v dc supply voltage v dd3.3 -0.3 to + 4.6 v dc supply voltage v ddq -0.3 to + 4.6 v dc voltage on any pin (note 3) v in -0.3 to + 5.5 v dc static discharge voltage 1000 v latch-up current 100 ma dc input current i in 20 ma lead temperature +230 c junction temperature t j +150 c notes on power supplies: 1. vdd3.3 and vddq should power up before vdd2.5. 2. vdd3.3 and vddq should not be allowed to drop below the vdd2.5 voltage level except when vdd2.5 is not powered. 3. all pins on the temap are 5v tolerant.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 202 15 d.c. characteristics t a = -40c to +85c, v dd3.3 = 3.3v 10%, v dd2.5 = 2.5v 8% (typical conditions: t a = 25c, v dd3.3 = 3.3v, v ddq = 3.3v, v dd2.5 = 2.5v) table 33 - d.c. characteristics symbol parameter min typ max units conditions vdd3.3 power supply 2.97 3.3 3.63 volts vddq power supply 2.97 3.3 3.63 volts vdd2.5 power supply 2.3 2.5 2.7 volts vil input low voltage -0.5 0.6 volts guaranteed input low voltage vih input high voltage 2.0 5.5 volts guaranteed input high voltage vol output or bidirectional low voltage 0.4 volts vdd = min, iol = -4ma for d[7:0], laoe, recvclk1, recvclk2, tclk, tpos/tdat, tneg/tmfp, rgapclk/rsclk, rdatao, rfpo/rmfpo, rovrhd, tfpo/tmfpo/tgapclk, sbiact iol = -8ma for sddata[7:0], sddp, sdpl, sdv5, sajust_req, sc1fp, lac1j1v1, ladata[7:0], ladp, lapl iol = -2ma for others. note 3 voh output or bidirectional high voltage 2.4 volts vdd = min, ioh = 4ma for d[7:0], laoe, recvclk1, recvclk2, tclk, tpos/tdat, tneg/tmfp, rgapclk/rsclk, rdatao, rfpo/rmfpo, rovrhd, tfpo/tmfpo/tgapclk, sbiact ioh = 8ma for sddata[7:0], sddp, sdpl, sdv5, sajust_req, sc1fp, lac1j1v1, ladata[7:0], ladp, lapl ioh = 2ma for others. note 3
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 203 symbol parameter min typ max units conditions vt+ reset input high voltage 2.0 5.5 volts ttl schmidt vt- reset input low voltage -0.2 0.6 volts vth reset input hysteresis voltage 1.2 0.5 volts iilpu input low current +10 +100 a vil = gnd. notes 1, 3,4 iihpu input high current -10 +10 a vih = vdd. notes 1, 3 iil input low current -10 +10 a vil = gnd. notes 2, 3 iih input high current -10 +10 a vih = vdd. notes 2, 3 cin input capacitance 5 pf excluding package, package typically 2 pf cout output capacitance 5 pf excluding package, package typically 2 pf cio bidirectional capacitance 5 pf excluding package, package typically 2 pf iddop1 operating current 45 285 ma ma vdd2.5 = 2.7v vdd3.3 = 3.63 v outputs unloaded, transmux mode (note 4) iddop2 operating current 45 370 ma ma vdd2.5 = 2.7v vdd3.3 = 3.63 v outputs unloaded, telecom to vt/tu mapping, sbi backplane ? t1/vt1.5 (note 4) iddop3 operating current 45 380 ma ma vdd2.5 = 2.7v vdd3.3 = 3.63 v outputs unloaded, telecom to vt/tu mapping, sbi backplane ? e1/tu12 (note 4) notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 204 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. typical values are given as a design aid. the product is not tested to the typical values given in the data sheet.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 205 16 microprocessor interface timing characteristics (t a = -40c to +85c, v dd3.3 = 3.3v 10%, v dd2.5 = 2.5v 8%) table 34: microprocessor interface read access symbol parameter min max units tsar address to valid read set-up time 10 ns thar address to valid read hold time 5 ns tsalr address to latch set-up time 10 ns thalr address to latch hold time 10 ns tvl valid latch pulse width 20 ns tslr latch to read set-up 0 ns thlr latch to read hold 5 ns tprd valid read to valid data propagation delay 40 ns tzrd valid read negated to output tri-state 20 ns tzinth valid read negated to output tri-state 50 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 206 figure 42: microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a [13:0] a le ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalr, thalr, tvl, and tslr are not applicable.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 207 5. parameter thar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 35: microprocessor interface write access symbol parameter min max units tsaw address to valid write set-up time 10 ns tsdw data to valid write set-up time 20 ns tsalw address to latch set-up time 10 ns thalw address to latch hold time 10 ns tvl valid latch pulse width 20 ns tslw latch to write set-up 0 ns thlw latch to write hold 5 ns thdw data to valid write hold time 5 ns thaw address to valid write hold time 5 ns tvwr valid write pulse width 40 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 208 figure 43: microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a [9:0] valid address a le tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalw, thalw, tvl, tslw and thlw are not applicable. 3. parameter thaw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 209 17 temap timing characteristics (t a = -40c to +85c v dd3.3 = 3.3v 10%, v dd2.5 = 2.5v 8%) table 36: rtsb timing symbol description min max units tvrstb rstb pulse width 100 ns figure 44: rstb timing table 37: ds3 transmit interface timing symbol description min max units f ticlk ticlk frequency 52 mhz t0 ticlk ticlk minimum pulse width low 7.7 ns t1 ticlk ticlk minimum pulse width high 7.7 ns ts tfpi tfpi/tmfpi to ticlk set-up time (loopt=0) tfpi/tmfpi to rclk set-up time (loopt=1) (see note 1) 5 5 ns th tfpi tfpi/tmfpi to ticlk hold time (loopt=0) tfpi/tmfpi to rclk hold time (loopt=1) (see note 2) 1 1 ns ts tdati tdati to ticlk set-up time (loopt = 0) tdati to rclk set-up time (loopt = 1) (see note 1) 5 5 ns th tdati tdati to ticlk hold time (loopt = 0) tdati to rclk hold time (loopt = 1) (see note 2) 1 1 ns tp tfpo ticlk high to tpfo prop delay (s n t 3 d 4) 2 16 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 210 (see note 3 and 4) ts tgap tdati to tgapclk set-up time (see notes 1 and 5) 3 ns th tgap tdati to tgapclk hold time (see note 2 and 5) 2 ns tp tclk ticlk edge to tclk edge prop delay (see notes 3 and 4) 2 13 ns tp tpos tclk edge to tpos/tdat prop delay (see notes 3 and 4) -1 5 ns tp tneg tclk edge to tneg/tmfp prop delay (see notes 3 and 4) -1 5 ns tp tpos2 ticlk high to tpos/tdat prop delay (see notes 3 and 4) 2 13 ns tp tneg2 ticlk high to tneg/tmfp prop delay (see notes 3 and 4) 2 13 ns notes on ds3 transmit interface timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum and minimum output propagation delays are measured with a 20 pf load on all the outputs. 5. setup and hold times relative to tgapclk are measured with a 20 pf load on atgapclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 211 figure 57: ds3 transmit interface timing ts tfpi th tfpi tfpi/tmfpi ticlk/rclk ts tdati th tdati tdati ticlk/rclk tp tfpo tfpo/tmfpo ticlk/rclk ts tgap th tgap tdati tgapclk
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 212 tp tneg tneg/tmfp ticlk tp tpos tpos/tdat tclk ticlk=0, trise=0 tp tneg tneg/tmfp ticlk tp tpos tpos/tdat tclk ticlk=0, trise=1 tp tneg2 tneg/tmfp ticlk tp tclk tp tpos2 tpos/tdat tclk tp tclk ticlk=1, trise= x
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 213 table 38: ds3 receive interface timing symbol description min max units f rclk rclk frequency 52 mhz t0 rclk rclk minimum pulse width low 7.7 ns t1 rclk rclk minimum pulse width high 7.7 ns ts rpos rpos/rdat set-up time (see note 1) 4 ns th rpos rpos/rdat hold time (see note 2) 1 ns ts rneg rneg/rlcv set-up time (see note 1) 4 ns th rneg rneg/rlcv hold time (see note 2) 1 ns tp rdato rsclk edge to rdato prop delay (see notes 3 and 4) 2 12 ns tp rfpo rsclk edge to rfpo/rmfpo prop delay (see notes 3 and 4) 2 12 ns tp rovrhd rsclk edge to rovrhd prop delay (see notes 3 and 4) 2 12 ns tp rgap rgapclk edge to rdato[x] prop delay (see notes 3 and 4) 3 11 ns notes on ds3 transmit interface timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum and minimum output propagation delays are measured with a 50 pf load on all the outputs.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 214 figure 58: ds3 receive interface timing ts rpos th rpos rpos/rdat rclk ts rneg th rneg rneg/rlcv tp rdato rdato tp rfpo rfpo/rmfpo rsclk tp rovrhd rovrhd dashed line rsclk represents behaviour when rsclkr register bit = 1.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 215 tp rgap rdato rgapclk dashed line rsclk represents behaviour when rsclkr register bit = 1. table 39: line side telecom bus input timing (figure 62) symbol description min max units lrefclk frequency 19.44 -20 ppm 19.44 +20 ppm mhz lrefclk duty cycle 40 60 % clk52m frequency (51.84 mhz) 51.84 -50 ppm 51.84 +50 ppm mhz clk52m frequency (44.928 mhz) 44.928 -50 ppm 44.928 +50 ppm mhz clk52m duty cycle 40 60 % ts tel all telecom bus inputs set-up time to lrefclk (see note 1) 5 ns th tel all telecom bus inputs hold time to lrefclk (see note 2) 1 ns notes on telecom input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 216 figure 59: line side telecom bus inputtiming lrefclk ts tel th tel lac1 lddata[7:0] lddp,ldpl ldtpl,ldais ldv5,ldc1j1 table 40 ? telecom bus output timing (figure 63 to figure 64) symbol description min max units t p tel lrefclk to all telecom bus outputs valid (see notes 1,2 and 4) 3 20 ns t z tel lrefclk to all telecom bus tristateable outputs going tristate (see note 3) 3 12 ns t p teloe lrefclk to all telecom bus tristateable outputs going valid from tristate (see notes 1,2 and 4) 3 20 ns notes on telecom bus output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs. 3. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 4. the propagation delay, t p tel , should be used when telecom bus outputs are always driven as configured by laddoe in register 1200h. the propagation delays, t p teloe and t z tel , should be used when the telecom bus outputs are multiplexed with other temap devices using the tristate capability of the outputs as configured by laddoe in register 1200h. note that consideration
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 217 of each individual pi n across the bus demonstrates that there are no reliability issues related to signal contention. figure 60: telecom bus output timing lrefclk ladata[7:0] ladp, lapl laoe tp tel lac1j1v1 figure 61: telecom bus tristate output timing lrefclk tp teloe tz tel ladata[7:0] ladp, lapl
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 218 table 41: sbi add bus timing (figure 62) symbol description min max units srefclk frequency (see note 6) 19.44 -50 ppm 19.44 +50 ppm mhz srefclk duty cycle 40 60 % ts sbiadd all sbi add bus inputs set-up time to srefclk (see note 1) 4 ns th sbiadd all sbi add bus inputs hold time to srefclk (see note 2) 0.75 ns t p sbiadd srefclk to sajust_req valid (see notes 3 and 4) 2 20 ns t z sbiadd srefclk to sajust_req tristate (see note 5) 2 20 ns notes on sbi input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs. 5. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 6. note that in transparent vt mode this clock must be connected to lrefclk. in this case, the more stringent specification of +/- 20ppm applies.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 219 figure 62: sbi add bus timing srefclk ts sbiadd th sbiadd sc1fp sadata[7:0] sadp,sapl sav5 sajust_req tp sbiadd tz sbiadd table 42 ? sbi drop bus timing (figure 63 to figure 64) symbol description min max units t p sbidrop srefclk to sbi drop bus outputs valid (see notes 1 and 2) 2 20 ns t p sbiact srefclk to sbiact output valid (see notes 1 and 3) 2 19 ns t z sbidrop srefclk to all sbi drop bus outputs tristate (see note 4) 2 12 ns t p outen sbidet[1] and sbidet[0] low to all sbi drop bus outputs valid (see notes 1 and 2) 2 15 ns t z outen sbidet[1] and sbidet[0] high to all sbi drop bus outputs tristate (see note 4) 2 12 ns ts det sbidet[n] set-up time to srefclk (see notes 5) 4 ns th det sbidet[n] hold time to srefclk (see notes 6) 0 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 220 notes on sbi output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs. 3. maximum and minimum output propagation delay is measured with a 50pf load. 4. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 5. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 6. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. figure 63: sbi drop bus timing srefclk sddata[7:0] sddp, sdpl sdv5 tp s bidrop tz sbidrop sddata[7:0] sddp, sdpl sdv5 sbiact tp s biact
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 221 figure 64: sbi drop bus collision avoidance timing sbidet[n] tp outen tz outen sddata[7:0] sddp, sdpl sdv5 ts det srefclk th det
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 222 table 43: xclk input (figure 65) symbol description min max units t l xclk xclk low pulse width 4 8 ns t h xclk xclk high pulse width 4 8 ns t xclk xclk period (typically 1/37.056 mhz 32 ppm for t1 operation or 1/49.152 mhz for e1 operation) 5 20 ns figure 65: xclk input timing
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 223 table 44: egress interface input timi ng - clock master : clear channel mode (figure 66) symbol description min max units tseclk eclk[x] to ed[x] set-up time 7,9 30 ns theclk eclk[x] to ed[x] hold time 8,9 30 ns figure 66: egress interface input timi ng - clock master : clear channel mode eclk[x] valid ts eclk th eclk ed[x] note: eclk[x] is an output derived from ctclk.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 224 table 45: egress interface input timing - clock slave : clear channel mode (figure 67) symbol description min max units tseclk eclk[x] to ed[x] set-up time 7,9 30 ns theclk eclk[x] to ed[x] hold time 8,9 30 ns figure 67: egress interface input timing - clock slave : clear channel mode eclk[x] v alid ts eclk th eclk ed[x] note: eclk[x] is an input.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 225 table 46: ingress interface timing - clock master modes (figure 68) symbol description min max units tp iclk iclk[x] to ingress output prop. delay 9,10,11 -20 20 ns figure 68: ingress interface timing - clock master modes iclk[x] valid tp iclk id[x] ifp[x]
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 226 table 47: transmit line interface timing (figure 69) symbol description min max units ctclk frequency (when used for tjat ref), typically 1.544 mhz 130 ppm for t1 operation or 2.048 mhz 50 ppm for e1 operation 2,3,6 1.5 2.1 mhz t h ctclk ctclk high duration 4 (when used for tjat ref) 100 ns t l ctclk ctclk low duration 4 (when used for tjat ref) 100 ns figure 69: transmit line interface timing ctclk t l t h t ctclk ctclk ctclk notes on ingress and egress serial interface timing: 1. guaranteed by design for nominal xclk input frequency (37.056 mhz 100 ppm for t1 modes and 49.152 mhz 50ppm for e1 modes). 2. ctclk can be a jittered clock signal subject to the minimum high and low times shown. these specifications correspond to nominal xclk input frequency of 37.056 mhz 100 ppm for t1 modes and 49.152 mhz 50ppm for e1 modes. 3. high pulse width is measured from the 1.4 volt points of the rise and fall ramps. low pulse width is measured from the 1.4 volt points of the fall and rise ramps. 4. xclk frequency must be 24x the line rate 32 ppm when tjat is free- running or referenced to a derivative of xclk. xclk may be 100 ppm if an accurate reference is provided to tjat.
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 227 5. ctclk can be a jittered clock signal subject to the minimum high and low durations thctclk, tlctclk. these durations correspond to nominal xclk input frequency. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 8. setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 9. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 10. output propagation delays are measured with a 50 pf load on all outputs with the exception of the high speed ds3 outputs (tclk, tpos/tdat, tneg/tmfp). the tclk, tpos/tdat, tneg/tmfp output propagation delays are measured with a 20 pf load. table 48: remote serial alarm port timing symbol description min max units radeastck and radwestck frequency 1.344 10 mhz radeastck and radwestck duty cycle 40 60 % t h radfp radeastfp and radwestfp hold time 5 ns t s radfp radeastfp and radwestfp setup time 5 ns t h rad radeast and radwest hold time 5 ns t s rad radeast and radwest setup time 5 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 228 figure 70: remote serial alarm port timing radeastck/ radwestck radeastfp/ radwestfp radeast/ radwest ts radfp th radfp ts rad th rad
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 229 table 49: jtag port interface symbol description min max units tck frequency 1 mhz tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 100 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 100 ns tp tdo tck low to tdo valid 2 100 ns tv trstb trstb pulse width 100 ns
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 230 figure 71: jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 231 18 ordering and thermal information table 50 - ordering and thermal information part no. description PM5365-PI 324 plastic ball grid array (pbga) table 51 - thermal information ? theta ja vs. airflow forced air (linear feet per minute) theta ja ( c/w) @ specified power convection 100 200 300 400 500 dense board 35.3 31.0 27.9 25.9 24.5 23.6 jedec board 20.5 18.8 17.7 16.8 16.3 15.8
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 232 19 mechanical information figure 72: 324 pin pbga 23x23mm body e a b c d e f g h j k l m n p r t u v w y aa ab b bottom view a1 ball corner j i "d" dia. 3 places 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 m m 0.30 c b 0.10 c a b a a1 ball indicator d d1 e1 e 0.20 (4x) 45 chamfer 4 places a1 ball pad corner top view a1 a c a2 seating plane bbb c c aaa c 30 typ side view notes: 1) all dimensions in millimeter. 2) dimension aaa denotes coplanarity. 3) dimension bbb denotes parallel. 23.00 19.00 19.50 20.20 1.00 1.00 0.63 0.50 0.70 2.07 2.28 2.49 1.82 2.03 2.22 0.40 0.50 0.60 1.12 1.17 1.22 23.00 19.00 19.50 20.20 0.36 0.61 1.00 1.00 0.15 0.35 0.30 0.40 0.55 0.67
standard product pm5365 temap datasheet pmc- 1991148 i ssue 3 high density vt/tu mapper and m13 multiplexer proprietary and confidential to pmc-sierra, inc. and for its customers? internal use 233 notes

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